b010affea4
Amdgpu driver uses 4-byte data type as DQM fence memory, and transmits GPU address of fence memory to microcode through query status PM4 message. However, query status PM4 message definition and microcode processing are all processed according to 8 bytes. Fence memory only allocates 4 bytes of memory, but microcode does write 8 bytes of memory, so there is a memory corruption. Changes since v1: * Change dqm->fence_addr as a u64 pointer to fix this issue, also fix up query_status and amdkfd_fence_wait_timeout function uses 64 bit fence value to make them consistent. Signed-off-by: Qu Huang <jinsdb@126.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
257 lines
8.7 KiB
C
257 lines
8.7 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef KFD_DEVICE_QUEUE_MANAGER_H_
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#define KFD_DEVICE_QUEUE_MANAGER_H_
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#include <linux/rwsem.h>
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#include <linux/list.h>
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#include <linux/mutex.h>
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#include <linux/sched/mm.h>
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#include "kfd_priv.h"
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#include "kfd_mqd_manager.h"
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#define VMID_NUM 16
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struct device_process_node {
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struct qcm_process_device *qpd;
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struct list_head list;
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};
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/**
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* struct device_queue_manager_ops
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*
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* @create_queue: Queue creation routine.
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*
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* @destroy_queue: Queue destruction routine.
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*
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* @update_queue: Queue update routine.
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*
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* @exeute_queues: Dispatches the queues list to the H/W.
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*
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* @register_process: This routine associates a specific process with device.
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*
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* @unregister_process: destroys the associations between process to device.
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*
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* @initialize: Initializes the pipelines and memory module for that device.
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*
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* @start: Initializes the resources/modules the the device needs for queues
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* execution. This function is called on device initialization and after the
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* system woke up after suspension.
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*
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* @stop: This routine stops execution of all the active queue running on the
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* H/W and basically this function called on system suspend.
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*
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* @uninitialize: Destroys all the device queue manager resources allocated in
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* initialize routine.
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*
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* @create_kernel_queue: Creates kernel queue. Used for debug queue.
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*
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* @destroy_kernel_queue: Destroys kernel queue. Used for debug queue.
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*
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* @set_cache_memory_policy: Sets memory policy (cached/ non cached) for the
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* memory apertures.
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*
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* @process_termination: Clears all process queues belongs to that device.
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*
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* @evict_process_queues: Evict all active queues of a process
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*
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* @restore_process_queues: Restore all evicted queues queues of a process
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*
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* @get_wave_state: Retrieves context save state and optionally copies the
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* control stack, if kept in the MQD, to the given userspace address.
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*/
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struct device_queue_manager_ops {
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int (*create_queue)(struct device_queue_manager *dqm,
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struct queue *q,
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struct qcm_process_device *qpd);
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int (*destroy_queue)(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd,
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struct queue *q);
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int (*update_queue)(struct device_queue_manager *dqm,
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struct queue *q);
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int (*register_process)(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd);
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int (*unregister_process)(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd);
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int (*initialize)(struct device_queue_manager *dqm);
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int (*start)(struct device_queue_manager *dqm);
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int (*stop)(struct device_queue_manager *dqm);
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void (*pre_reset)(struct device_queue_manager *dqm);
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void (*uninitialize)(struct device_queue_manager *dqm);
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int (*create_kernel_queue)(struct device_queue_manager *dqm,
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struct kernel_queue *kq,
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struct qcm_process_device *qpd);
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void (*destroy_kernel_queue)(struct device_queue_manager *dqm,
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struct kernel_queue *kq,
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struct qcm_process_device *qpd);
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bool (*set_cache_memory_policy)(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd,
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enum cache_policy default_policy,
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enum cache_policy alternate_policy,
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void __user *alternate_aperture_base,
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uint64_t alternate_aperture_size);
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int (*process_termination)(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd);
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int (*evict_process_queues)(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd);
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int (*restore_process_queues)(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd);
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int (*get_wave_state)(struct device_queue_manager *dqm,
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struct queue *q,
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void __user *ctl_stack,
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u32 *ctl_stack_used_size,
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u32 *save_area_used_size);
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};
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struct device_queue_manager_asic_ops {
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int (*update_qpd)(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd);
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bool (*set_cache_memory_policy)(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd,
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enum cache_policy default_policy,
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enum cache_policy alternate_policy,
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void __user *alternate_aperture_base,
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uint64_t alternate_aperture_size);
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void (*init_sdma_vm)(struct device_queue_manager *dqm,
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struct queue *q,
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struct qcm_process_device *qpd);
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struct mqd_manager * (*mqd_manager_init)(enum KFD_MQD_TYPE type,
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struct kfd_dev *dev);
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};
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/**
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* struct device_queue_manager
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*
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* This struct is a base class for the kfd queues scheduler in the
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* device level. The device base class should expose the basic operations
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* for queue creation and queue destruction. This base class hides the
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* scheduling mode of the driver and the specific implementation of the
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* concrete device. This class is the only class in the queues scheduler
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* that configures the H/W.
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*
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*/
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struct device_queue_manager {
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struct device_queue_manager_ops ops;
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struct device_queue_manager_asic_ops asic_ops;
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struct mqd_manager *mqd_mgrs[KFD_MQD_TYPE_MAX];
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struct packet_manager packets;
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struct kfd_dev *dev;
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struct mutex lock_hidden; /* use dqm_lock/unlock(dqm) */
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struct list_head queues;
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unsigned int saved_flags;
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unsigned int processes_count;
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unsigned int active_queue_count;
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unsigned int active_cp_queue_count;
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unsigned int gws_queue_count;
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unsigned int total_queue_count;
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unsigned int next_pipe_to_allocate;
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unsigned int *allocated_queues;
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uint64_t sdma_bitmap;
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uint64_t xgmi_sdma_bitmap;
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/* the pasid mapping for each kfd vmid */
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uint16_t vmid_pasid[VMID_NUM];
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uint64_t pipelines_addr;
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uint64_t fence_gpu_addr;
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uint64_t *fence_addr;
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struct kfd_mem_obj *fence_mem;
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bool active_runlist;
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int sched_policy;
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/* hw exception */
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bool is_hws_hang;
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bool is_resetting;
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struct work_struct hw_exception_work;
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struct kfd_mem_obj hiq_sdma_mqd;
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bool sched_running;
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};
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void device_queue_manager_init_cik(
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struct device_queue_manager_asic_ops *asic_ops);
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void device_queue_manager_init_cik_hawaii(
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struct device_queue_manager_asic_ops *asic_ops);
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void device_queue_manager_init_vi(
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struct device_queue_manager_asic_ops *asic_ops);
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void device_queue_manager_init_vi_tonga(
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struct device_queue_manager_asic_ops *asic_ops);
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void device_queue_manager_init_v9(
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struct device_queue_manager_asic_ops *asic_ops);
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void device_queue_manager_init_v10_navi10(
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struct device_queue_manager_asic_ops *asic_ops);
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void program_sh_mem_settings(struct device_queue_manager *dqm,
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struct qcm_process_device *qpd);
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unsigned int get_cp_queues_num(struct device_queue_manager *dqm);
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unsigned int get_queues_per_pipe(struct device_queue_manager *dqm);
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unsigned int get_pipes_per_mec(struct device_queue_manager *dqm);
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unsigned int get_num_sdma_queues(struct device_queue_manager *dqm);
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unsigned int get_num_xgmi_sdma_queues(struct device_queue_manager *dqm);
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static inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd)
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{
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return (pdd->lds_base >> 16) & 0xFF;
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}
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static inline unsigned int
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get_sh_mem_bases_nybble_64(struct kfd_process_device *pdd)
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{
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return (pdd->lds_base >> 60) & 0x0E;
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}
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/* The DQM lock can be taken in MMU notifiers. Make sure no reclaim-FS
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* happens while holding this lock anywhere to prevent deadlocks when
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* an MMU notifier runs in reclaim-FS context.
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*/
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static inline void dqm_lock(struct device_queue_manager *dqm)
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{
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mutex_lock(&dqm->lock_hidden);
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dqm->saved_flags = memalloc_noreclaim_save();
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}
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static inline void dqm_unlock(struct device_queue_manager *dqm)
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{
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memalloc_noreclaim_restore(dqm->saved_flags);
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mutex_unlock(&dqm->lock_hidden);
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}
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static inline int read_sdma_queue_counter(uint64_t __user *q_rptr, uint64_t *val)
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{
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/*
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* SDMA activity counter is stored at queue's RPTR + 0x8 location.
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*/
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return get_user(*val, q_rptr + 1);
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}
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#endif /* KFD_DEVICE_QUEUE_MANAGER_H_ */
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