Matthias Kaehlcke bf297420cc clk: rockchip: Limit use of USB PHY clock to USB on rk3288 ... The USB PHY clock can be configured as (grand) parent of uart0_sclk and sclk_gpu. It has been observed that UART0 doesn't work reliably in high speed mode with the PHY clock as input when certain USB devices are plugged to the USB HOST1 port (see https://crrev.com/c/320543). Prefix the name of the PHY clock with a '.' in the non-USB muxes to effectively remove the clock as input from these muxes. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>		2019-04-12 11:28:50 +02:00
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clk-cpu.c	clk: rockchip: Remove superfluous error message in rockchip_clk_register_cpuclk()	2017-09-28 15:22:50 +02:00
clk-ddr.c	clk: rockchip: Fix static checker warning in rockchip_ddrclk_get_parent call	2018-10-17 15:12:51 +02:00
clk-half-divider.c	clk: rockchip: add support for half divider	2018-07-06 19:17:57 +02:00
clk-inverter.c	clk: rockchip: don't return NULL when registering inverter fails	2016-02-15 23:35:20 +01:00
clk-mmc-phase.c	clk: rockchip: Fix error return in phase clock registration	2018-03-23 09:08:43 +01:00
clk-muxgrf.c	clk: rockchip: add a clock-type for muxes based in the grf	2017-01-02 14:24:57 +01:00
clk-pll.c	clk: rockchip: add pll_wait_lock for pll_enable	2017-03-22 18:33:22 +01:00
clk-px30.c	clk: rockchip: add clock controller for px30	2018-07-06 19:17:57 +02:00
clk-rk3036.c	clk: rockchip: mark pclk_ddrupctl as critical_clock on rk3036	2017-06-02 15:42:38 +02:00
clk-rk3128.c	clk: rockchip: add sclk_timer5 as critical clock on rk3128	2017-09-17 01:55:36 +02:00
clk-rk3188.c	clk: rockchip: add CLK_SET_RATE_PARENT for rk3066 lcdc dclks	2019-01-07 09:17:15 +01:00
clk-rk3228.c	clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228	2018-03-23 08:49:35 +01:00
clk-rk3288.c	clk: rockchip: Limit use of USB PHY clock to USB on rk3288	2019-04-12 11:28:50 +02:00
clk-rk3328.c	clk: rockchip: fix wrong clock definitions for rk3328	2019-03-18 08:45:55 +01:00
clk-rk3368.c	clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs	2017-10-14 21:31:58 +02:00
clk-rk3399.c	clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399	2018-08-06 23:46:52 +02:00
clk-rv1108.c	clk: rockchip: fix the rv1108 clk_mac sel register description	2017-08-22 02:55:03 +02:00
clk.c	clk: rockchip: add support for half divider	2018-07-06 19:17:57 +02:00
clk.h	clk: rockchip: add clock controller for px30	2018-07-06 19:17:57 +02:00
Makefile	clk: rockchip: add clock controller for px30	2018-07-06 19:17:57 +02:00
softrst.c	clk: rockchip: Make reset_control_ops const	2016-03-29 16:29:46 -07:00