forked from Minki/linux
beecadea1b
The macro bit(n) is defined as ((u32)1 << n), and thus it doesn't work
with n >= 32, such as in mvs_94xx_assign_reg_set():
if (i >= 32) {
mvi->sata_reg_set |= bit(i);
...
}
The shift ((u32)1 << n) with n >= 32 also leads to undefined behavior.
The result varies depending on the architecture.
This patch changes bit(n) to do a 64-bit shift. It also simplifies
mv_ffc64() using __ffs64(), since invoking ffz() with ~0 is undefined.
Signed-off-by: Xi Wang <xi.wang@gmail.com>
Acked-by: Xiangliang Yu <yuxiangl@marvell.com>
Cc: stable@vger.kernel.org
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
487 lines
13 KiB
C
487 lines
13 KiB
C
/*
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* Marvell 88SE64xx/88SE94xx main function head file
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*
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* Copyright 2007 Red Hat, Inc.
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* Copyright 2008 Marvell. <kewei@marvell.com>
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* Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
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*
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* This file is licensed under GPLv2.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the
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* License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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* USA
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*/
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#ifndef _MV_SAS_H_
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#define _MV_SAS_H_
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/delay.h>
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#include <linux/types.h>
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#include <linux/ctype.h>
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#include <linux/dma-mapping.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/slab.h>
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#include <linux/vmalloc.h>
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#include <scsi/libsas.h>
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#include <scsi/scsi.h>
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#include <scsi/scsi_tcq.h>
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#include <scsi/sas_ata.h>
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#include "mv_defs.h"
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#define DRV_NAME "mvsas"
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#define DRV_VERSION "0.8.16"
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#define MVS_ID_NOT_MAPPED 0x7f
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#define WIDE_PORT_MAX_PHY 4
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#define mv_printk(fmt, arg ...) \
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printk(KERN_DEBUG"%s %d:" fmt, __FILE__, __LINE__, ## arg)
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#ifdef MV_DEBUG
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#define mv_dprintk(format, arg...) \
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printk(KERN_DEBUG"%s %d:" format, __FILE__, __LINE__, ## arg)
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#else
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#define mv_dprintk(format, arg...)
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#endif
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#define MV_MAX_U32 0xffffffff
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extern int interrupt_coalescing;
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extern struct mvs_tgt_initiator mvs_tgt;
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extern struct mvs_info *tgt_mvi;
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extern const struct mvs_dispatch mvs_64xx_dispatch;
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extern const struct mvs_dispatch mvs_94xx_dispatch;
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extern struct kmem_cache *mvs_task_list_cache;
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#define DEV_IS_EXPANDER(type) \
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((type == EDGE_DEV) || (type == FANOUT_DEV))
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#define bit(n) ((u64)1 << n)
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#define for_each_phy(__lseq_mask, __mc, __lseq) \
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for ((__mc) = (__lseq_mask), (__lseq) = 0; \
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(__mc) != 0 ; \
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(++__lseq), (__mc) >>= 1)
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#define MV_INIT_DELAYED_WORK(w, f, d) INIT_DELAYED_WORK(w, f)
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#define UNASSOC_D2H_FIS(id) \
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((void *) mvi->rx_fis + 0x100 * id)
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#define SATA_RECEIVED_FIS_LIST(reg_set) \
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((void *) mvi->rx_fis + mvi->chip->fis_offs + 0x100 * reg_set)
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#define SATA_RECEIVED_SDB_FIS(reg_set) \
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(SATA_RECEIVED_FIS_LIST(reg_set) + 0x58)
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#define SATA_RECEIVED_D2H_FIS(reg_set) \
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(SATA_RECEIVED_FIS_LIST(reg_set) + 0x40)
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#define SATA_RECEIVED_PIO_FIS(reg_set) \
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(SATA_RECEIVED_FIS_LIST(reg_set) + 0x20)
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#define SATA_RECEIVED_DMA_FIS(reg_set) \
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(SATA_RECEIVED_FIS_LIST(reg_set) + 0x00)
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enum dev_status {
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MVS_DEV_NORMAL = 0x0,
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MVS_DEV_EH = 0x1,
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};
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enum dev_reset {
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MVS_SOFT_RESET = 0,
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MVS_HARD_RESET = 1,
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MVS_PHY_TUNE = 2,
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};
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struct mvs_info;
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struct mvs_dispatch {
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char *name;
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int (*chip_init)(struct mvs_info *mvi);
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int (*spi_init)(struct mvs_info *mvi);
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int (*chip_ioremap)(struct mvs_info *mvi);
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void (*chip_iounmap)(struct mvs_info *mvi);
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irqreturn_t (*isr)(struct mvs_info *mvi, int irq, u32 stat);
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u32 (*isr_status)(struct mvs_info *mvi, int irq);
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void (*interrupt_enable)(struct mvs_info *mvi);
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void (*interrupt_disable)(struct mvs_info *mvi);
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u32 (*read_phy_ctl)(struct mvs_info *mvi, u32 port);
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void (*write_phy_ctl)(struct mvs_info *mvi, u32 port, u32 val);
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u32 (*read_port_cfg_data)(struct mvs_info *mvi, u32 port);
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void (*write_port_cfg_data)(struct mvs_info *mvi, u32 port, u32 val);
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void (*write_port_cfg_addr)(struct mvs_info *mvi, u32 port, u32 addr);
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u32 (*read_port_vsr_data)(struct mvs_info *mvi, u32 port);
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void (*write_port_vsr_data)(struct mvs_info *mvi, u32 port, u32 val);
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void (*write_port_vsr_addr)(struct mvs_info *mvi, u32 port, u32 addr);
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u32 (*read_port_irq_stat)(struct mvs_info *mvi, u32 port);
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void (*write_port_irq_stat)(struct mvs_info *mvi, u32 port, u32 val);
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u32 (*read_port_irq_mask)(struct mvs_info *mvi, u32 port);
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void (*write_port_irq_mask)(struct mvs_info *mvi, u32 port, u32 val);
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void (*command_active)(struct mvs_info *mvi, u32 slot_idx);
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void (*clear_srs_irq)(struct mvs_info *mvi, u8 reg_set, u8 clear_all);
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void (*issue_stop)(struct mvs_info *mvi, enum mvs_port_type type,
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u32 tfs);
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void (*start_delivery)(struct mvs_info *mvi, u32 tx);
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u32 (*rx_update)(struct mvs_info *mvi);
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void (*int_full)(struct mvs_info *mvi);
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u8 (*assign_reg_set)(struct mvs_info *mvi, u8 *tfs);
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void (*free_reg_set)(struct mvs_info *mvi, u8 *tfs);
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u32 (*prd_size)(void);
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u32 (*prd_count)(void);
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void (*make_prd)(struct scatterlist *scatter, int nr, void *prd);
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void (*detect_porttype)(struct mvs_info *mvi, int i);
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int (*oob_done)(struct mvs_info *mvi, int i);
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void (*fix_phy_info)(struct mvs_info *mvi, int i,
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struct sas_identify_frame *id);
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void (*phy_work_around)(struct mvs_info *mvi, int i);
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void (*phy_set_link_rate)(struct mvs_info *mvi, u32 phy_id,
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struct sas_phy_linkrates *rates);
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u32 (*phy_max_link_rate)(void);
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void (*phy_disable)(struct mvs_info *mvi, u32 phy_id);
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void (*phy_enable)(struct mvs_info *mvi, u32 phy_id);
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void (*phy_reset)(struct mvs_info *mvi, u32 phy_id, int hard);
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void (*stp_reset)(struct mvs_info *mvi, u32 phy_id);
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void (*clear_active_cmds)(struct mvs_info *mvi);
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u32 (*spi_read_data)(struct mvs_info *mvi);
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void (*spi_write_data)(struct mvs_info *mvi, u32 data);
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int (*spi_buildcmd)(struct mvs_info *mvi,
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u32 *dwCmd,
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u8 cmd,
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u8 read,
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u8 length,
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u32 addr
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);
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int (*spi_issuecmd)(struct mvs_info *mvi, u32 cmd);
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int (*spi_waitdataready)(struct mvs_info *mvi, u32 timeout);
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void (*dma_fix)(struct mvs_info *mvi, u32 phy_mask,
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int buf_len, int from, void *prd);
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void (*tune_interrupt)(struct mvs_info *mvi, u32 time);
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void (*non_spec_ncq_error)(struct mvs_info *mvi);
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};
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struct mvs_chip_info {
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u32 n_host;
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u32 n_phy;
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u32 fis_offs;
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u32 fis_count;
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u32 srs_sz;
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u32 sg_width;
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u32 slot_width;
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const struct mvs_dispatch *dispatch;
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};
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#define MVS_MAX_SG (1U << mvi->chip->sg_width)
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#define MVS_CHIP_SLOT_SZ (1U << mvi->chip->slot_width)
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#define MVS_RX_FISL_SZ \
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(mvi->chip->fis_offs + (mvi->chip->fis_count * 0x100))
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#define MVS_CHIP_DISP (mvi->chip->dispatch)
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struct mvs_err_info {
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__le32 flags;
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__le32 flags2;
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};
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struct mvs_cmd_hdr {
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__le32 flags; /* PRD tbl len; SAS, SATA ctl */
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__le32 lens; /* cmd, max resp frame len */
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__le32 tags; /* targ port xfer tag; tag */
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__le32 data_len; /* data xfer len */
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__le64 cmd_tbl; /* command table address */
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__le64 open_frame; /* open addr frame address */
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__le64 status_buf; /* status buffer address */
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__le64 prd_tbl; /* PRD tbl address */
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__le32 reserved[4];
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};
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struct mvs_port {
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struct asd_sas_port sas_port;
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u8 port_attached;
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u8 wide_port_phymap;
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struct list_head list;
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};
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struct mvs_phy {
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struct mvs_info *mvi;
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struct mvs_port *port;
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struct asd_sas_phy sas_phy;
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struct sas_identify identify;
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struct scsi_device *sdev;
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struct timer_list timer;
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u64 dev_sas_addr;
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u64 att_dev_sas_addr;
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u32 att_dev_info;
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u32 dev_info;
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u32 phy_type;
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u32 phy_status;
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u32 irq_status;
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u32 frame_rcvd_size;
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u8 frame_rcvd[32];
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u8 phy_attached;
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u8 phy_mode;
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u8 reserved[2];
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u32 phy_event;
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enum sas_linkrate minimum_linkrate;
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enum sas_linkrate maximum_linkrate;
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};
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struct mvs_device {
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struct list_head dev_entry;
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enum sas_dev_type dev_type;
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struct mvs_info *mvi_info;
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struct domain_device *sas_device;
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struct timer_list timer;
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u32 attached_phy;
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u32 device_id;
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u32 running_req;
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u8 taskfileset;
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u8 dev_status;
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u16 reserved;
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};
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/* Generate PHY tunning parameters */
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struct phy_tuning {
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/* 1 bit, transmitter emphasis enable */
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u8 trans_emp_en:1;
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/* 4 bits, transmitter emphasis amplitude */
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u8 trans_emp_amp:4;
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/* 3 bits, reserved space */
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u8 Reserved_2bit_1:3;
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/* 5 bits, transmitter amplitude */
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u8 trans_amp:5;
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/* 2 bits, transmitter amplitude adjust */
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u8 trans_amp_adj:2;
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/* 1 bit, reserved space */
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u8 resv_2bit_2:1;
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/* 2 bytes, reserved space */
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u8 reserved[2];
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};
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struct ffe_control {
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/* 4 bits, FFE Capacitor Select (value range 0~F) */
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u8 ffe_cap_sel:4;
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/* 3 bits, FFE Resistor Select (value range 0~7) */
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u8 ffe_rss_sel:3;
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/* 1 bit reserve*/
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u8 reserved:1;
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};
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/*
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* HBA_Info_Page is saved in Flash/NVRAM, total 256 bytes.
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* The data area is valid only Signature="MRVL".
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* If any member fills with 0xFF, the member is invalid.
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*/
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struct hba_info_page {
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/* Dword 0 */
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/* 4 bytes, structure signature,should be "MRVL" at first initial */
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u8 signature[4];
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/* Dword 1-13 */
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u32 reserved1[13];
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/* Dword 14-29 */
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/* 64 bytes, SAS address for each port */
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u64 sas_addr[8];
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/* Dword 30-31 */
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/* 8 bytes for vanir 8 port PHY FFE seeting
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* BIT 0~3 : FFE Capacitor select(value range 0~F)
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* BIT 4~6 : FFE Resistor select(value range 0~7)
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* BIT 7: reserve.
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*/
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struct ffe_control ffe_ctl[8];
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/* Dword 32 -43 */
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u32 reserved2[12];
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/* Dword 44-45 */
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/* 8 bytes, 0: 1.5G, 1: 3.0G, should be 0x01 at first initial */
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u8 phy_rate[8];
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/* Dword 46-53 */
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/* 32 bytes, PHY tuning parameters for each PHY*/
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struct phy_tuning phy_tuning[8];
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/* Dword 54-63 */
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u32 reserved3[10];
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}; /* total 256 bytes */
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struct mvs_slot_info {
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struct list_head entry;
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union {
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struct sas_task *task;
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void *tdata;
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};
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u32 n_elem;
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u32 tx;
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u32 slot_tag;
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/* DMA buffer for storing cmd tbl, open addr frame, status buffer,
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* and PRD table
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*/
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void *buf;
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dma_addr_t buf_dma;
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void *response;
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struct mvs_port *port;
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struct mvs_device *device;
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void *open_frame;
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};
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struct mvs_info {
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unsigned long flags;
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/* host-wide lock */
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spinlock_t lock;
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/* our device */
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struct pci_dev *pdev;
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struct device *dev;
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/* enhanced mode registers */
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void __iomem *regs;
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/* peripheral or soc registers */
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void __iomem *regs_ex;
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u8 sas_addr[SAS_ADDR_SIZE];
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/* SCSI/SAS glue */
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struct sas_ha_struct *sas;
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struct Scsi_Host *shost;
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/* TX (delivery) DMA ring */
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__le32 *tx;
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dma_addr_t tx_dma;
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/* cached next-producer idx */
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u32 tx_prod;
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/* RX (completion) DMA ring */
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__le32 *rx;
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dma_addr_t rx_dma;
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/* RX consumer idx */
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u32 rx_cons;
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/* RX'd FIS area */
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__le32 *rx_fis;
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dma_addr_t rx_fis_dma;
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/* DMA command header slots */
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struct mvs_cmd_hdr *slot;
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dma_addr_t slot_dma;
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u32 chip_id;
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const struct mvs_chip_info *chip;
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int tags_num;
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unsigned long *tags;
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/* further per-slot information */
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struct mvs_phy phy[MVS_MAX_PHYS];
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struct mvs_port port[MVS_MAX_PHYS];
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u32 id;
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u64 sata_reg_set;
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struct list_head *hba_list;
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struct list_head soc_entry;
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struct list_head wq_list;
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unsigned long instance;
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u16 flashid;
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u32 flashsize;
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u32 flashsectSize;
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void *addon;
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struct hba_info_page hba_info_param;
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struct mvs_device devices[MVS_MAX_DEVICES];
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void *bulk_buffer;
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dma_addr_t bulk_buffer_dma;
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void *bulk_buffer1;
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dma_addr_t bulk_buffer_dma1;
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#define TRASH_BUCKET_SIZE 0x20000
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void *dma_pool;
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struct mvs_slot_info slot_info[0];
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};
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struct mvs_prv_info{
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u8 n_host;
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u8 n_phy;
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u8 scan_finished;
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u8 reserve;
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struct mvs_info *mvi[2];
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struct tasklet_struct mv_tasklet;
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};
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struct mvs_wq {
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struct delayed_work work_q;
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struct mvs_info *mvi;
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void *data;
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int handler;
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struct list_head entry;
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};
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struct mvs_task_exec_info {
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struct sas_task *task;
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struct mvs_cmd_hdr *hdr;
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struct mvs_port *port;
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u32 tag;
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int n_elem;
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};
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struct mvs_task_list {
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struct sas_task *task;
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struct list_head list;
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};
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/******************** function prototype *********************/
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void mvs_get_sas_addr(void *buf, u32 buflen);
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void mvs_tag_clear(struct mvs_info *mvi, u32 tag);
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void mvs_tag_free(struct mvs_info *mvi, u32 tag);
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void mvs_tag_set(struct mvs_info *mvi, unsigned int tag);
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int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out);
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void mvs_tag_init(struct mvs_info *mvi);
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void mvs_iounmap(void __iomem *regs);
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int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex);
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void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard);
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int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
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void *funcdata);
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void __devinit mvs_set_sas_addr(struct mvs_info *mvi, int port_id,
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u32 off_lo, u32 off_hi, u64 sas_addr);
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void mvs_scan_start(struct Scsi_Host *shost);
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int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time);
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int mvs_queue_command(struct sas_task *task, const int num,
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gfp_t gfp_flags);
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int mvs_abort_task(struct sas_task *task);
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int mvs_abort_task_set(struct domain_device *dev, u8 *lun);
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int mvs_clear_aca(struct domain_device *dev, u8 *lun);
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int mvs_clear_task_set(struct domain_device *dev, u8 * lun);
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void mvs_port_formed(struct asd_sas_phy *sas_phy);
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void mvs_port_deformed(struct asd_sas_phy *sas_phy);
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int mvs_dev_found(struct domain_device *dev);
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void mvs_dev_gone(struct domain_device *dev);
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int mvs_lu_reset(struct domain_device *dev, u8 *lun);
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int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags);
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int mvs_I_T_nexus_reset(struct domain_device *dev);
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int mvs_query_task(struct sas_task *task);
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void mvs_release_task(struct mvs_info *mvi,
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struct domain_device *dev);
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void mvs_do_release_task(struct mvs_info *mvi, int phy_no,
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struct domain_device *dev);
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void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events);
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void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st);
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int mvs_int_rx(struct mvs_info *mvi, bool self_clear);
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struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi, u8 reg_set);
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#endif
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