forked from Minki/linux
755a9ba7bf
As with previous release, this continues to be among the largest branches we merge, with lots of new contents. New things for this release are among other things: - DTSI contents for the new SoCs supported in 3.16 (see SoC pull request) - Qualcomm APQ8064 and APQ8084 SoCs and eval boards - Nvidia Jetson TK1 development board (Tegra T124-based) Two new SoCs that didn't need enough new platform code to stand out enough for me to notice when writing the SoC tag, but that adds new DT contents are: - TI DRA72 - Marvell Berlin 2Q -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJTjNNQAAoJEIwa5zzehBx3KyYP/3TEJcXXEYDURXDB0SktPNyy cKp5HUnsu4+aq/Ae6jdjVGiX5FZa64Xije9b0kP3oxoPS+fuODvzhlnoEsT84Ab5 /jeygWJZYUIWAQTxShPT55K8WAEtL7H1WcvswdCZoTDxPBNCLR/nLzv084nv9Die IOUWDTKW4qB8+KYQxh2TBx0E1TorZ0J5OWf6qqepZ0i4J5dhL1VYtc/ZNU5C37V5 rZyyBQNOCBE/MK/Dw9CnResQf4f8DigHBYgpl7VxB+bBqfgzFuSSEPvg21MXLkfi ln64yYTVvqhleVjGriDV+mUHOCZr4sUWZPDzeF5HzpvqDAMDWTsWlHNh6WDU6dgo b+zFPqqnWaBiWrinY+o7MVvjVzu3Nf8id/GyjnDJEFbSc9ka/8uiC3v9UJXAFawF 3Huc3K6BC/3qOoCPfnBotzx7Xxxvjk2lPRfnonhSvBoSzPeFc6vz2k4USX1GbdkB y/v+Q+n52VebxiKknTMv9HOI06yTOJo2ji+2iKIULb+W86HzNRZL8ZlmNib4WysF z/OgHZl+YzbhJQJtvfBecCIH2Hu+A4GD2ES8hhklA0QhFHPiDfB9cqcsthSGS5oL dDaGv6XGpHoySlEm1ybgWhvH96dc7lTR+nPGZqCKtRBn5pJiEHczxQ2Jz3aBHYeW PUPlrVfYXzIKsh+OU1HO =OvOG -----END PGP SIGNATURE----- Merge tag 'dt-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next Pull ARM SoC devicetree updates from Olof Johansson: "As with previous release, this continues to be among the largest branches we merge, with lots of new contents. New things for this release are among other things: - DTSI contents for the new SoCs supported in 3.16 (see SoC pull request) - Qualcomm APQ8064 and APQ8084 SoCs and eval boards - Nvidia Jetson TK1 development board (Tegra T124-based) Two new SoCs that didn't need enough new platform code to stand out enough for me to notice when writing the SoC tag, but that adds new DT contents are: - TI DRA72 - Marvell Berlin 2Q" * tag 'dt-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (500 commits) ARM: dts: add secure firmware support for exynos5420-arndale-octa ARM: dts: add pmu sysreg node to exynos3250 ARM: dts: correct the usb phy node in exynos5800-peach-pi ARM: dts: correct the usb phy node in exynos5420-peach-pit ARM: dts: add dts files for exynos5410 and exynos5410-smdk5410 ARM: dts: add dts files for exynos3250 SoC ARM: dts: add mfc node for exynos5800 ARM: dts: add Vbus regulator for USB 3.0 on exynos5800-peach-pi ARM: dts: enable fimd for exynos5800-peach-pi ARM: dts: enable display controller for exynos5800-peach-pi ARM: dts: enable hdmi for exynos5800-peach-pi ARM: dts: add dts file for exynos5800-peach-pi board ARM: dts: add dts file for exynos5800 SoC ARM: dts: add dts file for exynos5260-xyref5260 board ARM: dts: add dts files for exynos5260 SoC ARM: dts: update watchdog node name in exynos5440 ARM: dts: use key code macros on Origen and Arndale boards ARM: dts: enable RTC and WDT nodes on Origen boards ARM: dts: qcom: Add APQ8084-MTP board support ARM: dts: qcom: Add APQ8084 SoC support ...
267 lines
5.9 KiB
Plaintext
267 lines
5.9 KiB
Plaintext
/*
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include "rk3xxx.dtsi"
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#include "rk3188-clocks.dtsi"
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/ {
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compatible = "rockchip,rk3188";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "rockchip,rk3066-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x3>;
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};
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};
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soc {
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global-timer@1013c200 {
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interrupts = <GIC_PPI 11 0xf04>;
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};
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local-timer@1013c600 {
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interrupts = <GIC_PPI 13 0xf04>;
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};
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sram: sram@10080000 {
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compatible = "mmio-sram";
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reg = <0x10080000 0x8000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x10080000 0x8000>;
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smp-sram@0 {
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compatible = "rockchip,rk3066-smp-sram";
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reg = <0x0 0x50>;
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};
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};
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pinctrl@20008000 {
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compatible = "rockchip,rk3188-pinctrl";
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rockchip,grf = <&grf>;
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rockchip,pmu = <&pmu>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio0: gpio0@0x2000a000 {
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compatible = "rockchip,rk3188-gpio-bank0";
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reg = <0x2000a000 0x100>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates8 9>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio1@0x2003c000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x2003c000 0x100>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates8 10>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio2@2003e000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x2003e000 0x100>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates8 11>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio3@20080000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x20080000 0x100>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates8 12>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pcfg_pull_up: pcfg_pull_up {
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bias-pull-up;
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};
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pcfg_pull_down: pcfg_pull_down {
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bias-pull-down;
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};
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pcfg_pull_none: pcfg_pull_none {
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bias-disable;
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};
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uart0 {
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uart0_xfer: uart0-xfer {
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rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
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<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart0_cts: uart0-cts {
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rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart0_rts: uart0-rts {
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rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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uart1 {
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uart1_xfer: uart1-xfer {
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rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
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<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart1_cts: uart1-cts {
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rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart1_rts: uart1-rts {
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rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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uart2 {
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uart2_xfer: uart2-xfer {
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rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
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<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
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};
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/* no rts / cts for uart2 */
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};
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uart3 {
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uart3_xfer: uart3-xfer {
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rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
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<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart3_cts: uart3-cts {
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rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart3_rts: uart3-rts {
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rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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sd0 {
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sd0_clk: sd0-clk {
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rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd0_cmd: sd0-cmd {
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rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd0_cd: sd0-cd {
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rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd0_wp: sd0-wp {
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rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd0_pwr: sd0-pwr {
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rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd0_bus1: sd0-bus-width1 {
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rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd0_bus4: sd0-bus-width4 {
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rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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sd1 {
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sd1_clk: sd1-clk {
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rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd1_cmd: sd1-cmd {
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rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd1_cd: sd1-cd {
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rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd1_wp: sd1-wp {
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rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd1_bus1: sd1-bus-width1 {
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rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd1_bus4: sd1-bus-width4 {
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rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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};
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};
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};
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