forked from Minki/linux
e120fb4596
After clarification from the hardware team it was found that this 1.8V PHY supply can't be switched OFF when SoC is Active. Since the PHY IPs don't contain isolation logic built in the design to allow the power rail to be switched off, there is a very high risk of IP reliability and additional leakage paths which can result in additional power consumption. The only scenario where this rail can be switched off is part of Power on reset sequencing, but it needs to be kept always-on during operation. This patch is required for proper functionality of USB, SATA and PCIe on DRA7-evm. CC: Rajendra Nayak <rnayak@ti.com> CC: Tero Kristo <t-kristo@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
499 lines
12 KiB
Plaintext
499 lines
12 KiB
Plaintext
/*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include "dra74x.dtsi"
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/ {
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model = "TI DRA742";
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compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
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memory {
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device_type = "memory";
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reg = <0x80000000 0x60000000>; /* 1536 MB */
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};
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mmc2_3v3: fixedregulator-mmc2 {
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compatible = "regulator-fixed";
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regulator-name = "mmc2_3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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&dra7_pmx_core {
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i2c1_pins: pinmux_i2c1_pins {
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pinctrl-single,pins = <
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0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
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0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
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>;
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};
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i2c2_pins: pinmux_i2c2_pins {
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pinctrl-single,pins = <
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0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
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0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
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>;
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};
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i2c3_pins: pinmux_i2c3_pins {
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pinctrl-single,pins = <
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0x410 (PIN_INPUT | MUX_MODE0) /* i2c3_sda */
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0x414 (PIN_INPUT | MUX_MODE0) /* i2c3_scl */
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>;
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};
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mcspi1_pins: pinmux_mcspi1_pins {
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pinctrl-single,pins = <
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0x3a4 (PIN_INPUT | MUX_MODE0) /* spi2_clk */
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0x3a8 (PIN_INPUT | MUX_MODE0) /* spi2_d1 */
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0x3ac (PIN_INPUT | MUX_MODE0) /* spi2_d0 */
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0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
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0x3b4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs1 */
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0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs2 */
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0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs3 */
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>;
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};
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mcspi2_pins: pinmux_mcspi2_pins {
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pinctrl-single,pins = <
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0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
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0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
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0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
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0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
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>;
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};
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uart1_pins: pinmux_uart1_pins {
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pinctrl-single,pins = <
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0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
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0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
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0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
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0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
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>;
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};
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uart2_pins: pinmux_uart2_pins {
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pinctrl-single,pins = <
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0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
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0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
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0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
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0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
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>;
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};
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uart3_pins: pinmux_uart3_pins {
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pinctrl-single,pins = <
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0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
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0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
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>;
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};
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qspi1_pins: pinmux_qspi1_pins {
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pinctrl-single,pins = <
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0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
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0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
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0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
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0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
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0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
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0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
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0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
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0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
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0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
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0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
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>;
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};
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usb1_pins: pinmux_usb1_pins {
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pinctrl-single,pins = <
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0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
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>;
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};
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usb2_pins: pinmux_usb2_pins {
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pinctrl-single,pins = <
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0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
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>;
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};
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nand_flash_x16: nand_flash_x16 {
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/* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
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* So NAND flash requires following switch settings:
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* SW5.9 (GPMC_WPN) = LOW
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* SW5.1 (NAND_BOOTn) = HIGH */
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pinctrl-single,pins = <
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0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
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0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
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0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
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0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
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0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
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0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
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0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
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0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
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0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
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0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
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0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
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0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
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0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
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0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
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0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
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0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
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0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
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0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
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0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
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0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
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0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
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0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
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>;
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};
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};
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&i2c1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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clock-frequency = <400000>;
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tps659038: tps659038@58 {
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compatible = "ti,tps659038";
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reg = <0x58>;
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tps659038_pmic {
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compatible = "ti,tps659038-pmic";
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regulators {
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smps123_reg: smps123 {
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/* VDD_MPU */
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regulator-name = "smps123";
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regulator-min-microvolt = < 850000>;
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regulator-max-microvolt = <1250000>;
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regulator-always-on;
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regulator-boot-on;
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};
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smps45_reg: smps45 {
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/* VDD_DSPEVE */
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regulator-name = "smps45";
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regulator-min-microvolt = < 850000>;
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regulator-max-microvolt = <1150000>;
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regulator-boot-on;
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};
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smps6_reg: smps6 {
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/* VDD_GPU - over VDD_SMPS6 */
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regulator-name = "smps6";
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <12500000>;
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regulator-boot-on;
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};
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smps7_reg: smps7 {
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/* CORE_VDD */
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regulator-name = "smps7";
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <1030000>;
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regulator-always-on;
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regulator-boot-on;
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};
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smps8_reg: smps8 {
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/* VDD_IVAHD */
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regulator-name = "smps8";
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regulator-min-microvolt = < 850000>;
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regulator-max-microvolt = <1250000>;
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regulator-boot-on;
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};
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smps9_reg: smps9 {
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/* VDDS1V8 */
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regulator-name = "smps9";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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ldo1_reg: ldo1 {
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/* LDO1_OUT --> SDIO */
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regulator-name = "ldo1";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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ldo2_reg: ldo2 {
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/* VDD_RTCIO */
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/* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
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regulator-name = "ldo2";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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ldo3_reg: ldo3 {
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/* VDDA_1V8_PHY */
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regulator-name = "ldo3";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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ldo9_reg: ldo9 {
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/* VDD_RTC */
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regulator-name = "ldo9";
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regulator-min-microvolt = <1050000>;
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regulator-max-microvolt = <1050000>;
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regulator-boot-on;
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};
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ldoln_reg: ldoln {
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/* VDDA_1V8_PLL */
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regulator-name = "ldoln";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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ldousb_reg: ldousb {
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/* VDDA_3V_USB: VDDA_USBHS33 */
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regulator-name = "ldousb";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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};
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};
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};
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};
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&i2c2 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_pins>;
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clock-frequency = <400000>;
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};
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&i2c3 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3_pins>;
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clock-frequency = <3400000>;
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};
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&mcspi1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&mcspi1_pins>;
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};
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&mcspi2 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&mcspi2_pins>;
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};
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&uart1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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};
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&uart2 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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};
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&uart3 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&uart3_pins>;
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};
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&mmc1 {
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status = "okay";
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vmmc-supply = <&ldo1_reg>;
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bus-width = <4>;
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};
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&mmc2 {
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status = "okay";
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vmmc-supply = <&mmc2_3v3>;
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bus-width = <8>;
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};
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&cpu0 {
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cpu0-supply = <&smps123_reg>;
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};
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&qspi {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&qspi1_pins>;
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spi-max-frequency = <48000000>;
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m25p80@0 {
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compatible = "s25fl256s1";
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spi-max-frequency = <48000000>;
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reg = <0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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spi-cpol;
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spi-cpha;
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#address-cells = <1>;
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#size-cells = <1>;
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/* MTD partition table.
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* The ROM checks the first four physical blocks
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* for a valid file to boot and the flash here is
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* 64KiB block size.
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*/
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partition@0 {
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label = "QSPI.SPL";
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reg = <0x00000000 0x000010000>;
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};
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partition@1 {
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label = "QSPI.SPL.backup1";
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reg = <0x00010000 0x00010000>;
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};
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partition@2 {
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label = "QSPI.SPL.backup2";
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reg = <0x00020000 0x00010000>;
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};
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partition@3 {
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label = "QSPI.SPL.backup3";
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reg = <0x00030000 0x00010000>;
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};
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partition@4 {
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label = "QSPI.u-boot";
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reg = <0x00040000 0x00100000>;
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};
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partition@5 {
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label = "QSPI.u-boot-spl-os";
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reg = <0x00140000 0x00010000>;
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};
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partition@6 {
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label = "QSPI.u-boot-env";
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reg = <0x00150000 0x00010000>;
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};
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partition@7 {
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label = "QSPI.u-boot-env.backup1";
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reg = <0x00160000 0x0010000>;
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};
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partition@8 {
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label = "QSPI.kernel";
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reg = <0x00170000 0x0800000>;
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};
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partition@9 {
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label = "QSPI.file-system";
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reg = <0x00970000 0x01690000>;
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};
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};
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};
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&usb1 {
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dr_mode = "peripheral";
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pinctrl-names = "default";
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pinctrl-0 = <&usb1_pins>;
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};
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&usb2 {
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dr_mode = "host";
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pinctrl-names = "default";
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pinctrl-0 = <&usb2_pins>;
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};
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&elm {
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status = "okay";
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};
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&gpmc {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&nand_flash_x16>;
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ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
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nand@0,0 {
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reg = <0 0 4>; /* device IO registers */
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ti,nand-ecc-opt = "bch8";
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ti,elm-id = <&elm>;
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nand-bus-width = <16>;
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gpmc,device-width = <2>;
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gpmc,sync-clk-ps = <0>;
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gpmc,cs-on-ns = <0>;
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gpmc,cs-rd-off-ns = <40>;
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gpmc,cs-wr-off-ns = <40>;
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gpmc,adv-on-ns = <0>;
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gpmc,adv-rd-off-ns = <30>;
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gpmc,adv-wr-off-ns = <30>;
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gpmc,we-on-ns = <5>;
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gpmc,we-off-ns = <25>;
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gpmc,oe-on-ns = <2>;
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gpmc,oe-off-ns = <20>;
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gpmc,access-ns = <20>;
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gpmc,wr-access-ns = <40>;
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gpmc,rd-cycle-ns = <40>;
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gpmc,wr-cycle-ns = <40>;
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gpmc,wait-pin = <0>;
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gpmc,wait-on-read;
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gpmc,wait-on-write;
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <0>;
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gpmc,clk-activation-ns = <0>;
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gpmc,wait-monitoring-ns = <0>;
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gpmc,wr-data-mux-bus-ns = <0>;
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/* MTD partition table */
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/* All SPL-* partitions are sized to minimal length
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* which can be independently programmable. For
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* NAND flash this is equal to size of erase-block */
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
|
|
label = "NAND.SPL";
|
|
reg = <0x00000000 0x000020000>;
|
|
};
|
|
partition@1 {
|
|
label = "NAND.SPL.backup1";
|
|
reg = <0x00020000 0x00020000>;
|
|
};
|
|
partition@2 {
|
|
label = "NAND.SPL.backup2";
|
|
reg = <0x00040000 0x00020000>;
|
|
};
|
|
partition@3 {
|
|
label = "NAND.SPL.backup3";
|
|
reg = <0x00060000 0x00020000>;
|
|
};
|
|
partition@4 {
|
|
label = "NAND.u-boot-spl-os";
|
|
reg = <0x00080000 0x00040000>;
|
|
};
|
|
partition@5 {
|
|
label = "NAND.u-boot";
|
|
reg = <0x000c0000 0x00100000>;
|
|
};
|
|
partition@6 {
|
|
label = "NAND.u-boot-env";
|
|
reg = <0x001c0000 0x00020000>;
|
|
};
|
|
partition@7 {
|
|
label = "NAND.u-boot-env";
|
|
reg = <0x001e0000 0x00020000>;
|
|
};
|
|
partition@8 {
|
|
label = "NAND.kernel";
|
|
reg = <0x00200000 0x00800000>;
|
|
};
|
|
partition@9 {
|
|
label = "NAND.file-system";
|
|
reg = <0x00a00000 0x0f600000>;
|
|
};
|
|
};
|
|
};
|