Jake Wang bdfc6fd6c8 drm/amd/display: Update dram_clock_change_latency for DCN2.1 ... [WHY] dram clock change latencies get updated using ddr4 latency table, but that update does not happen before validation. This value should not be the default and should be number received from df for better mode support. This may cause a PState hang on high refresh panels with short vblanks such as on 1080p 360hz or 300hz panels. [HOW] Update latency from 23.84 to 11.72. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Jake Wang <haonan.wang2@amd.com> Reviewed-by: Sung Lee <Sung.Lee@amd.com> Acked-by: Anson Jacob <anson.jacob@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-01-21 10:46:05 -05:00
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drm	drm/amd/display: Update dram_clock_change_latency for DCN2.1	2021-01-21 10:46:05 -05:00
host1x	gpu/host1x: bus: Add missing description for 'driver'	2020-11-05 22:12:55 +01:00
ipu-v3	gpu: ipu-v3: remove unused functions	2020-10-26 10:42:38 +01:00
trace
vga	pci-v5.11-changes	2020-12-15 16:49:59 -08:00
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