forked from Minki/linux
bd6f82d828
A basic, no-frills recovery mechanism in case the gpu gets wedged. We could try to be a bit more fancy and restart the next submit after the one that got wedged, but for now keep it simple. This is enough to recover things if, for example, the gpu hangs mid way through a piglit run. Signed-off-by: Rob Clark <robdclark@gmail.com>
503 lines
16 KiB
C
503 lines
16 KiB
C
/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "a3xx_gpu.h"
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#define A3XX_INT0_MASK \
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(A3XX_INT0_RBBM_AHB_ERROR | \
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A3XX_INT0_RBBM_ATB_BUS_OVERFLOW | \
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A3XX_INT0_CP_T0_PACKET_IN_IB | \
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A3XX_INT0_CP_OPCODE_ERROR | \
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A3XX_INT0_CP_RESERVED_BIT_ERROR | \
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A3XX_INT0_CP_HW_FAULT | \
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A3XX_INT0_CP_IB1_INT | \
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A3XX_INT0_CP_IB2_INT | \
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A3XX_INT0_CP_RB_INT | \
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A3XX_INT0_CP_REG_PROTECT_FAULT | \
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A3XX_INT0_CP_AHB_ERROR_HALT | \
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A3XX_INT0_UCHE_OOB_ACCESS)
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static struct platform_device *a3xx_pdev;
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static void a3xx_me_init(struct msm_gpu *gpu)
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{
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struct msm_ringbuffer *ring = gpu->rb;
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OUT_PKT3(ring, CP_ME_INIT, 17);
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OUT_RING(ring, 0x000003f7);
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OUT_RING(ring, 0x00000000);
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OUT_RING(ring, 0x00000000);
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OUT_RING(ring, 0x00000000);
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OUT_RING(ring, 0x00000080);
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OUT_RING(ring, 0x00000100);
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OUT_RING(ring, 0x00000180);
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OUT_RING(ring, 0x00006600);
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OUT_RING(ring, 0x00000150);
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OUT_RING(ring, 0x0000014e);
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OUT_RING(ring, 0x00000154);
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OUT_RING(ring, 0x00000001);
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OUT_RING(ring, 0x00000000);
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OUT_RING(ring, 0x00000000);
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OUT_RING(ring, 0x00000000);
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OUT_RING(ring, 0x00000000);
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OUT_RING(ring, 0x00000000);
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gpu->funcs->flush(gpu);
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gpu->funcs->idle(gpu);
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}
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static int a3xx_hw_init(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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uint32_t *ptr, len;
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int i, ret;
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DBG("%s", gpu->name);
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if (adreno_is_a305(adreno_gpu)) {
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/* Set up 16 deep read/write request queues: */
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gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010);
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gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x10101010);
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gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x10101010);
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gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x10101010);
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gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303);
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gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x10101010);
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gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x10101010);
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/* Enable WR-REQ: */
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gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x0000ff);
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/* Set up round robin arbitration between both AXI ports: */
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gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030);
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/* Set up AOOO: */
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gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c);
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gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c);
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} else if (adreno_is_a320(adreno_gpu)) {
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/* Set up 16 deep read/write request queues: */
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gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010);
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gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x10101010);
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gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x10101010);
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gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x10101010);
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gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303);
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gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x10101010);
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gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x10101010);
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/* Enable WR-REQ: */
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gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x0000ff);
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/* Set up round robin arbitration between both AXI ports: */
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gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030);
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/* Set up AOOO: */
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gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c);
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gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c);
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/* Enable 1K sort: */
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gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x000000ff);
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gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4);
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} else if (adreno_is_a330(adreno_gpu)) {
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/* Set up 16 deep read/write request queues: */
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gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x18181818);
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gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x18181818);
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gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x18181818);
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gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x18181818);
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gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303);
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gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x18181818);
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gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x18181818);
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/* Enable WR-REQ: */
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gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x00003f);
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/* Set up round robin arbitration between both AXI ports: */
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gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030);
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/* Set up VBIF_ROUND_ROBIN_QOS_ARB: */
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gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0001);
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/* Set up AOOO: */
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gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000ffff);
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gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0xffffffff);
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/* Enable 1K sort: */
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gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x0001ffff);
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gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4);
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/* Disable VBIF clock gating. This is to enable AXI running
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* higher frequency than GPU:
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*/
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gpu_write(gpu, REG_A3XX_VBIF_CLKON, 0x00000001);
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} else {
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BUG();
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}
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/* Make all blocks contribute to the GPU BUSY perf counter: */
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gpu_write(gpu, REG_A3XX_RBBM_GPU_BUSY_MASKED, 0xffffffff);
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/* Tune the hystersis counters for SP and CP idle detection: */
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gpu_write(gpu, REG_A3XX_RBBM_SP_HYST_CNT, 0x10);
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gpu_write(gpu, REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL, 0x10);
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/* Enable the RBBM error reporting bits. This lets us get
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* useful information on failure:
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*/
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gpu_write(gpu, REG_A3XX_RBBM_AHB_CTL0, 0x00000001);
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/* Enable AHB error reporting: */
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gpu_write(gpu, REG_A3XX_RBBM_AHB_CTL1, 0xa6ffffff);
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/* Turn on the power counters: */
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gpu_write(gpu, REG_A3XX_RBBM_RBBM_CTL, 0x00030000);
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/* Turn on hang detection - this spews a lot of useful information
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* into the RBBM registers on a hang:
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*/
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gpu_write(gpu, REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL, 0x00010fff);
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/* Enable 64-byte cacheline size. HW Default is 32-byte (0x000000E0): */
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gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001);
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/* Enable Clock gating: */
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gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff);
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/* Set the OCMEM base address for A330 */
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//TODO:
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// if (adreno_is_a330(adreno_gpu)) {
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// gpu_write(gpu, REG_A3XX_RB_GMEM_BASE_ADDR,
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// (unsigned int)(a3xx_gpu->ocmem_base >> 14));
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// }
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/* Turn on performance counters: */
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gpu_write(gpu, REG_A3XX_RBBM_PERFCTR_CTL, 0x01);
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/* Set SP perfcounter 7 to count SP_FS_FULL_ALU_INSTRUCTIONS
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* we will use this to augment our hang detection:
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*/
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gpu_write(gpu, REG_A3XX_SP_PERFCOUNTER7_SELECT,
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SP_FS_FULL_ALU_INSTRUCTIONS);
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gpu_write(gpu, REG_A3XX_RBBM_INT_0_MASK, A3XX_INT0_MASK);
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ret = adreno_hw_init(gpu);
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if (ret)
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return ret;
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/* setup access protection: */
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gpu_write(gpu, REG_A3XX_CP_PROTECT_CTRL, 0x00000007);
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/* RBBM registers */
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gpu_write(gpu, REG_A3XX_CP_PROTECT(0), 0x63000040);
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gpu_write(gpu, REG_A3XX_CP_PROTECT(1), 0x62000080);
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gpu_write(gpu, REG_A3XX_CP_PROTECT(2), 0x600000cc);
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gpu_write(gpu, REG_A3XX_CP_PROTECT(3), 0x60000108);
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gpu_write(gpu, REG_A3XX_CP_PROTECT(4), 0x64000140);
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gpu_write(gpu, REG_A3XX_CP_PROTECT(5), 0x66000400);
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/* CP registers */
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gpu_write(gpu, REG_A3XX_CP_PROTECT(6), 0x65000700);
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gpu_write(gpu, REG_A3XX_CP_PROTECT(7), 0x610007d8);
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gpu_write(gpu, REG_A3XX_CP_PROTECT(8), 0x620007e0);
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gpu_write(gpu, REG_A3XX_CP_PROTECT(9), 0x61001178);
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gpu_write(gpu, REG_A3XX_CP_PROTECT(10), 0x64001180);
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/* RB registers */
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gpu_write(gpu, REG_A3XX_CP_PROTECT(11), 0x60003300);
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/* VBIF registers */
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gpu_write(gpu, REG_A3XX_CP_PROTECT(12), 0x6b00c000);
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/* NOTE: PM4/micro-engine firmware registers look to be the same
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* for a2xx and a3xx.. we could possibly push that part down to
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* adreno_gpu base class. Or push both PM4 and PFP but
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* parameterize the pfp ucode addr/data registers..
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*/
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/* Load PM4: */
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ptr = (uint32_t *)(adreno_gpu->pm4->data);
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len = adreno_gpu->pm4->size / 4;
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DBG("loading PM4 ucode version: %u", ptr[0]);
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gpu_write(gpu, REG_AXXX_CP_DEBUG,
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AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE |
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AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE);
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gpu_write(gpu, REG_AXXX_CP_ME_RAM_WADDR, 0);
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for (i = 1; i < len; i++)
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gpu_write(gpu, REG_AXXX_CP_ME_RAM_DATA, ptr[i]);
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/* Load PFP: */
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ptr = (uint32_t *)(adreno_gpu->pfp->data);
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len = adreno_gpu->pfp->size / 4;
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DBG("loading PFP ucode version: %u", ptr[0]);
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gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_ADDR, 0);
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for (i = 1; i < len; i++)
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gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_DATA, ptr[i]);
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/* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */
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if (adreno_is_a305(adreno_gpu) || adreno_is_a320(adreno_gpu))
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gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS,
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AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(2) |
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AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(6) |
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AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(14));
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/* clear ME_HALT to start micro engine */
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gpu_write(gpu, REG_AXXX_CP_ME_CNTL, 0);
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a3xx_me_init(gpu);
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return 0;
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}
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static void a3xx_destroy(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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struct a3xx_gpu *a3xx_gpu = to_a3xx_gpu(adreno_gpu);
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DBG("%s", gpu->name);
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adreno_gpu_cleanup(adreno_gpu);
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put_device(&a3xx_gpu->pdev->dev);
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kfree(a3xx_gpu);
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}
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static void a3xx_idle(struct msm_gpu *gpu)
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{
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unsigned long t;
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/* wait for ringbuffer to drain: */
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adreno_idle(gpu);
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t = jiffies + ADRENO_IDLE_TIMEOUT;
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/* then wait for GPU to finish: */
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do {
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uint32_t rbbm_status = gpu_read(gpu, REG_A3XX_RBBM_STATUS);
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if (!(rbbm_status & A3XX_RBBM_STATUS_GPU_BUSY))
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return;
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} while(time_before(jiffies, t));
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DRM_ERROR("timeout waiting for %s to idle!\n", gpu->name);
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/* TODO maybe we need to reset GPU here to recover from hang? */
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}
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static irqreturn_t a3xx_irq(struct msm_gpu *gpu)
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{
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uint32_t status;
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status = gpu_read(gpu, REG_A3XX_RBBM_INT_0_STATUS);
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DBG("%s: %08x", gpu->name, status);
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// TODO
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gpu_write(gpu, REG_A3XX_RBBM_INT_CLEAR_CMD, status);
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msm_gpu_retire(gpu);
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return IRQ_HANDLED;
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}
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#ifdef CONFIG_DEBUG_FS
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static const unsigned int a3xx_registers[] = {
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0x0000, 0x0002, 0x0010, 0x0012, 0x0018, 0x0018, 0x0020, 0x0027,
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0x0029, 0x002b, 0x002e, 0x0033, 0x0040, 0x0042, 0x0050, 0x005c,
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0x0060, 0x006c, 0x0080, 0x0082, 0x0084, 0x0088, 0x0090, 0x00e5,
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0x00ea, 0x00ed, 0x0100, 0x0100, 0x0110, 0x0123, 0x01c0, 0x01c1,
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0x01c3, 0x01c5, 0x01c7, 0x01c7, 0x01d5, 0x01d9, 0x01dc, 0x01dd,
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0x01ea, 0x01ea, 0x01ee, 0x01f1, 0x01f5, 0x01f5, 0x01fc, 0x01ff,
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0x0440, 0x0440, 0x0443, 0x0443, 0x0445, 0x0445, 0x044d, 0x044f,
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0x0452, 0x0452, 0x0454, 0x046f, 0x047c, 0x047c, 0x047f, 0x047f,
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0x0578, 0x057f, 0x0600, 0x0602, 0x0605, 0x0607, 0x060a, 0x060e,
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0x0612, 0x0614, 0x0c01, 0x0c02, 0x0c06, 0x0c1d, 0x0c3d, 0x0c3f,
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0x0c48, 0x0c4b, 0x0c80, 0x0c80, 0x0c88, 0x0c8b, 0x0ca0, 0x0cb7,
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0x0cc0, 0x0cc1, 0x0cc6, 0x0cc7, 0x0ce4, 0x0ce5, 0x0e00, 0x0e05,
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0x0e0c, 0x0e0c, 0x0e22, 0x0e23, 0x0e41, 0x0e45, 0x0e64, 0x0e65,
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0x0e80, 0x0e82, 0x0e84, 0x0e89, 0x0ea0, 0x0ea1, 0x0ea4, 0x0ea7,
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0x0ec4, 0x0ecb, 0x0ee0, 0x0ee0, 0x0f00, 0x0f01, 0x0f03, 0x0f09,
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0x2040, 0x2040, 0x2044, 0x2044, 0x2048, 0x204d, 0x2068, 0x2069,
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0x206c, 0x206d, 0x2070, 0x2070, 0x2072, 0x2072, 0x2074, 0x2075,
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0x2079, 0x207a, 0x20c0, 0x20d3, 0x20e4, 0x20ef, 0x2100, 0x2109,
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0x210c, 0x210c, 0x210e, 0x210e, 0x2110, 0x2111, 0x2114, 0x2115,
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0x21e4, 0x21e4, 0x21ea, 0x21ea, 0x21ec, 0x21ed, 0x21f0, 0x21f0,
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0x2200, 0x2212, 0x2214, 0x2217, 0x221a, 0x221a, 0x2240, 0x227e,
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0x2280, 0x228b, 0x22c0, 0x22c0, 0x22c4, 0x22ce, 0x22d0, 0x22d8,
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0x22df, 0x22e6, 0x22e8, 0x22e9, 0x22ec, 0x22ec, 0x22f0, 0x22f7,
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0x22ff, 0x22ff, 0x2340, 0x2343, 0x2348, 0x2349, 0x2350, 0x2356,
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0x2360, 0x2360, 0x2440, 0x2440, 0x2444, 0x2444, 0x2448, 0x244d,
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0x2468, 0x2469, 0x246c, 0x246d, 0x2470, 0x2470, 0x2472, 0x2472,
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0x2474, 0x2475, 0x2479, 0x247a, 0x24c0, 0x24d3, 0x24e4, 0x24ef,
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0x2500, 0x2509, 0x250c, 0x250c, 0x250e, 0x250e, 0x2510, 0x2511,
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0x2514, 0x2515, 0x25e4, 0x25e4, 0x25ea, 0x25ea, 0x25ec, 0x25ed,
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0x25f0, 0x25f0, 0x2600, 0x2612, 0x2614, 0x2617, 0x261a, 0x261a,
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0x2640, 0x267e, 0x2680, 0x268b, 0x26c0, 0x26c0, 0x26c4, 0x26ce,
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0x26d0, 0x26d8, 0x26df, 0x26e6, 0x26e8, 0x26e9, 0x26ec, 0x26ec,
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0x26f0, 0x26f7, 0x26ff, 0x26ff, 0x2740, 0x2743, 0x2748, 0x2749,
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0x2750, 0x2756, 0x2760, 0x2760, 0x300c, 0x300e, 0x301c, 0x301d,
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0x302a, 0x302a, 0x302c, 0x302d, 0x3030, 0x3031, 0x3034, 0x3036,
|
|
0x303c, 0x303c, 0x305e, 0x305f,
|
|
};
|
|
|
|
static void a3xx_show(struct msm_gpu *gpu, struct seq_file *m)
|
|
{
|
|
int i;
|
|
|
|
adreno_show(gpu, m);
|
|
seq_printf(m, "status: %08x\n",
|
|
gpu_read(gpu, REG_A3XX_RBBM_STATUS));
|
|
|
|
/* dump these out in a form that can be parsed by demsm: */
|
|
seq_printf(m, "IO:region %s 00000000 00020000\n", gpu->name);
|
|
for (i = 0; i < ARRAY_SIZE(a3xx_registers); i += 2) {
|
|
uint32_t start = a3xx_registers[i];
|
|
uint32_t end = a3xx_registers[i+1];
|
|
uint32_t addr;
|
|
|
|
for (addr = start; addr <= end; addr++) {
|
|
uint32_t val = gpu_read(gpu, addr);
|
|
seq_printf(m, "IO:R %08x %08x\n", addr<<2, val);
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
|
|
static const struct adreno_gpu_funcs funcs = {
|
|
.base = {
|
|
.get_param = adreno_get_param,
|
|
.hw_init = a3xx_hw_init,
|
|
.pm_suspend = msm_gpu_pm_suspend,
|
|
.pm_resume = msm_gpu_pm_resume,
|
|
.recover = adreno_recover,
|
|
.last_fence = adreno_last_fence,
|
|
.submit = adreno_submit,
|
|
.flush = adreno_flush,
|
|
.idle = a3xx_idle,
|
|
.irq = a3xx_irq,
|
|
.destroy = a3xx_destroy,
|
|
#ifdef CONFIG_DEBUG_FS
|
|
.show = a3xx_show,
|
|
#endif
|
|
},
|
|
};
|
|
|
|
struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
|
|
{
|
|
struct a3xx_gpu *a3xx_gpu = NULL;
|
|
struct msm_gpu *gpu;
|
|
struct platform_device *pdev = a3xx_pdev;
|
|
struct adreno_platform_config *config;
|
|
int ret;
|
|
|
|
if (!pdev) {
|
|
dev_err(dev->dev, "no a3xx device\n");
|
|
ret = -ENXIO;
|
|
goto fail;
|
|
}
|
|
|
|
config = pdev->dev.platform_data;
|
|
|
|
a3xx_gpu = kzalloc(sizeof(*a3xx_gpu), GFP_KERNEL);
|
|
if (!a3xx_gpu) {
|
|
ret = -ENOMEM;
|
|
goto fail;
|
|
}
|
|
|
|
gpu = &a3xx_gpu->base.base;
|
|
|
|
get_device(&pdev->dev);
|
|
a3xx_gpu->pdev = pdev;
|
|
|
|
gpu->fast_rate = config->fast_rate;
|
|
gpu->slow_rate = config->slow_rate;
|
|
gpu->bus_freq = config->bus_freq;
|
|
|
|
DBG("fast_rate=%u, slow_rate=%u, bus_freq=%u",
|
|
gpu->fast_rate, gpu->slow_rate, gpu->bus_freq);
|
|
|
|
ret = adreno_gpu_init(dev, pdev, &a3xx_gpu->base,
|
|
&funcs, config->rev);
|
|
if (ret)
|
|
goto fail;
|
|
|
|
return &a3xx_gpu->base.base;
|
|
|
|
fail:
|
|
if (a3xx_gpu)
|
|
a3xx_destroy(&a3xx_gpu->base.base);
|
|
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
/*
|
|
* The a3xx device:
|
|
*/
|
|
|
|
static int a3xx_probe(struct platform_device *pdev)
|
|
{
|
|
static struct adreno_platform_config config = {};
|
|
#ifdef CONFIG_OF
|
|
/* TODO */
|
|
#else
|
|
uint32_t version = socinfo_get_version();
|
|
if (cpu_is_apq8064ab()) {
|
|
config.fast_rate = 450000000;
|
|
config.slow_rate = 27000000;
|
|
config.bus_freq = 4;
|
|
config.rev = ADRENO_REV(3, 2, 1, 0);
|
|
} else if (cpu_is_apq8064() || cpu_is_msm8960ab()) {
|
|
config.fast_rate = 400000000;
|
|
config.slow_rate = 27000000;
|
|
config.bus_freq = 4;
|
|
|
|
if (SOCINFO_VERSION_MAJOR(version) == 2)
|
|
config.rev = ADRENO_REV(3, 2, 0, 2);
|
|
else if ((SOCINFO_VERSION_MAJOR(version) == 1) &&
|
|
(SOCINFO_VERSION_MINOR(version) == 1))
|
|
config.rev = ADRENO_REV(3, 2, 0, 1);
|
|
else
|
|
config.rev = ADRENO_REV(3, 2, 0, 0);
|
|
|
|
} else if (cpu_is_msm8930()) {
|
|
config.fast_rate = 400000000;
|
|
config.slow_rate = 27000000;
|
|
config.bus_freq = 3;
|
|
|
|
if ((SOCINFO_VERSION_MAJOR(version) == 1) &&
|
|
(SOCINFO_VERSION_MINOR(version) == 2))
|
|
config.rev = ADRENO_REV(3, 0, 5, 2);
|
|
else
|
|
config.rev = ADRENO_REV(3, 0, 5, 0);
|
|
|
|
}
|
|
#endif
|
|
pdev->dev.platform_data = &config;
|
|
a3xx_pdev = pdev;
|
|
return 0;
|
|
}
|
|
|
|
static int a3xx_remove(struct platform_device *pdev)
|
|
{
|
|
a3xx_pdev = NULL;
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver a3xx_driver = {
|
|
.probe = a3xx_probe,
|
|
.remove = a3xx_remove,
|
|
.driver.name = "kgsl-3d0",
|
|
};
|
|
|
|
void __init a3xx_register(void)
|
|
{
|
|
platform_driver_register(&a3xx_driver);
|
|
}
|
|
|
|
void __exit a3xx_unregister(void)
|
|
{
|
|
platform_driver_unregister(&a3xx_driver);
|
|
}
|