forked from Minki/linux
a8064d577d
The CMP PCH ID we have in the driver is correct for the CML-U machines we have in our CI system, but the CML-S and CML-H CI machines appear to use a different PCH ID, leading our driver to detect no PCH for them. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> References:729ae330a0("drm/i915/cml: Introduce Comet Lake PCH") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111461 Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190916233251.387-1-matthew.d.roper@intel.com Fixes:729ae330a0("drm/i915/cml: Introduce Comet Lake PCH") (cherry picked from commit8698ba53cd) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
75 lines
3.0 KiB
C
75 lines
3.0 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright 2019 Intel Corporation.
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*/
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#ifndef __INTEL_PCH__
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#define __INTEL_PCH__
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struct drm_i915_private;
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/*
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* Sorted by south display engine compatibility.
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* If the new PCH comes with a south display engine that is not
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* inherited from the latest item, please do not add it to the
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* end. Instead, add it right after its "parent" PCH.
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*/
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enum intel_pch {
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PCH_NOP = -1, /* PCH without south display */
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PCH_NONE = 0, /* No PCH present */
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PCH_IBX, /* Ibexpeak PCH */
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PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
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PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
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PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */
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PCH_CNP, /* Cannon/Comet Lake PCH */
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PCH_ICP, /* Ice Lake PCH */
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PCH_MCC, /* Mule Creek Canyon PCH */
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PCH_TGP, /* Tiger Lake PCH */
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};
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#define INTEL_PCH_DEVICE_ID_MASK 0xff80
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#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
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#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
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#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
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#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
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#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
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#define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
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#define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
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#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
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#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
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#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
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#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
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#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
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#define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280
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#define INTEL_PCH_CMP2_DEVICE_ID_TYPE 0x0680
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#define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
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#define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00
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#define INTEL_PCH_MCC2_DEVICE_ID_TYPE 0x3880
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#define INTEL_PCH_TGP_DEVICE_ID_TYPE 0xA080
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#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
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#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
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#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
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#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
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#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
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#define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
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#define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
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#define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
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#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
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#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
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#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
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#define HAS_PCH_LPT_LP(dev_priv) \
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(INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
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INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
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#define HAS_PCH_LPT_H(dev_priv) \
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(INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
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INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
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#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
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#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
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#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
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#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
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void intel_detect_pch(struct drm_i915_private *dev_priv);
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#endif /* __INTEL_PCH__ */
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