bcd9a325f0
When platform_clock_control() first selects PLL1 as sysclk the PLL_CTRL registers have not been setup yet and we effectively have an invalid clock configuration until byt_rt5640_aif1_hw_params() gets called. Add a new byt_rt5640_prepare_and_enable_pll1() helper and use that from both platform_clock_control() and byt_rt5640_aif1_hw_params() to fix this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Mark Brown <broonie@kernel.org> |
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| atom | ||
| baytrail | ||
| boards | ||
| common | ||
| haswell | ||
| skylake | ||
| Kconfig | ||
| Makefile | ||