forked from Minki/linux
bcd644e046
Just move the lowfreq_avail logic out of the register writing as a prep step for the next patch, which will coalesce all the pch pll enabling into one spot. Note that writing the reduced clock dividers to FP1 in a few more cases (as this patch ends up doing) isn't really relevant since the FP1 value only matters when we enable the low lock. Which despite can only happen if we've actually enabled the reduced dotclock and furthermore isn't even properly implemented on ilk+: Despite claims to the contrary in the code switching between frequencies if fully manual. v2: Explain matters around the FP1 change to answer a question Damien raised in his review. Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
||
|---|---|---|
| .. | ||
| drm | ||
| host1x | ||
| vga | ||
| Makefile | ||