forked from Minki/linux
7847777a45
After changing all consumers of atomics to include <linux/atomic.h>, we
ran into some compile time errors due to this dependency chain:
linux/atomic.h
-> asm/atomic.h
-> asm-generic/atomic-long.h
where atomic-long.h could use funcs defined later in linux/atomic.h
without a prototype. This patches moves the code that includes
asm-generic/atomic*.h to linux/atomic.h.
Archs that need <asm-generic/atomic64.h> need to select
CONFIG_GENERIC_ATOMIC64 from now on (some of them used to include it
unconditionally).
Compile tested on i386 and x86_64 with allnoconfig.
Signed-off-by: Arun Sharma <asharma@fb.com>
Cc: Eric Dumazet <eric.dumazet@gmail.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: David Miller <davem@davemloft.net>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
476 lines
9.1 KiB
C
476 lines
9.1 KiB
C
#ifndef _ASM_POWERPC_ATOMIC_H_
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#define _ASM_POWERPC_ATOMIC_H_
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/*
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* PowerPC atomic operations
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*/
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#include <linux/types.h>
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#ifdef __KERNEL__
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#include <linux/compiler.h>
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#include <asm/synch.h>
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#include <asm/asm-compat.h>
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#include <asm/system.h>
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#define ATOMIC_INIT(i) { (i) }
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static __inline__ int atomic_read(const atomic_t *v)
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{
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int t;
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__asm__ __volatile__("lwz%U1%X1 %0,%1" : "=r"(t) : "m"(v->counter));
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return t;
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}
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static __inline__ void atomic_set(atomic_t *v, int i)
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{
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__asm__ __volatile__("stw%U0%X0 %1,%0" : "=m"(v->counter) : "r"(i));
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}
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static __inline__ void atomic_add(int a, atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%3 # atomic_add\n\
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add %0,%2,%0\n"
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PPC405_ERR77(0,%3)
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" stwcx. %0,0,%3 \n\
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bne- 1b"
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: "=&r" (t), "+m" (v->counter)
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: "r" (a), "r" (&v->counter)
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: "cc");
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}
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static __inline__ int atomic_add_return(int a, atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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PPC_RELEASE_BARRIER
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"1: lwarx %0,0,%2 # atomic_add_return\n\
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add %0,%1,%0\n"
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PPC405_ERR77(0,%2)
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" stwcx. %0,0,%2 \n\
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bne- 1b"
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PPC_ACQUIRE_BARRIER
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: "=&r" (t)
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: "r" (a), "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
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static __inline__ void atomic_sub(int a, atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%3 # atomic_sub\n\
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subf %0,%2,%0\n"
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PPC405_ERR77(0,%3)
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" stwcx. %0,0,%3 \n\
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bne- 1b"
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: "=&r" (t), "+m" (v->counter)
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: "r" (a), "r" (&v->counter)
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: "cc");
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}
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static __inline__ int atomic_sub_return(int a, atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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PPC_RELEASE_BARRIER
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"1: lwarx %0,0,%2 # atomic_sub_return\n\
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subf %0,%1,%0\n"
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PPC405_ERR77(0,%2)
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" stwcx. %0,0,%2 \n\
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bne- 1b"
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PPC_ACQUIRE_BARRIER
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: "=&r" (t)
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: "r" (a), "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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static __inline__ void atomic_inc(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 # atomic_inc\n\
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addic %0,%0,1\n"
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PPC405_ERR77(0,%2)
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" stwcx. %0,0,%2 \n\
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bne- 1b"
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: "=&r" (t), "+m" (v->counter)
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: "r" (&v->counter)
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: "cc", "xer");
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}
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static __inline__ int atomic_inc_return(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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PPC_RELEASE_BARRIER
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"1: lwarx %0,0,%1 # atomic_inc_return\n\
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addic %0,%0,1\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1 \n\
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bne- 1b"
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PPC_ACQUIRE_BARRIER
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: "=&r" (t)
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: "r" (&v->counter)
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: "cc", "xer", "memory");
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return t;
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}
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/*
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* atomic_inc_and_test - increment and test
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* @v: pointer of type atomic_t
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*
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* Atomically increments @v by 1
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* and returns true if the result is zero, or false for all
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* other cases.
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*/
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#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
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static __inline__ void atomic_dec(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 # atomic_dec\n\
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addic %0,%0,-1\n"
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PPC405_ERR77(0,%2)\
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" stwcx. %0,0,%2\n\
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bne- 1b"
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: "=&r" (t), "+m" (v->counter)
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: "r" (&v->counter)
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: "cc", "xer");
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}
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static __inline__ int atomic_dec_return(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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PPC_RELEASE_BARRIER
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"1: lwarx %0,0,%1 # atomic_dec_return\n\
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addic %0,%0,-1\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1\n\
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bne- 1b"
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PPC_ACQUIRE_BARRIER
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: "=&r" (t)
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: "r" (&v->counter)
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: "cc", "xer", "memory");
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return t;
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}
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#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
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#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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/**
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* __atomic_add_unless - add unless the number is a given value
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* @v: pointer of type atomic_t
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* @a: the amount to add to v...
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* @u: ...unless v is equal to u.
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*
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* Atomically adds @a to @v, so long as it was not @u.
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* Returns the old value of @v.
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*/
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static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
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{
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int t;
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__asm__ __volatile__ (
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PPC_RELEASE_BARRIER
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"1: lwarx %0,0,%1 # __atomic_add_unless\n\
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cmpw 0,%0,%3 \n\
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beq- 2f \n\
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add %0,%2,%0 \n"
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PPC405_ERR77(0,%2)
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" stwcx. %0,0,%1 \n\
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bne- 1b \n"
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PPC_ACQUIRE_BARRIER
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" subf %0,%2,%0 \n\
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2:"
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: "=&r" (t)
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: "r" (&v->counter), "r" (a), "r" (u)
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: "cc", "memory");
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return t;
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}
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#define atomic_sub_and_test(a, v) (atomic_sub_return((a), (v)) == 0)
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#define atomic_dec_and_test(v) (atomic_dec_return((v)) == 0)
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/*
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* Atomically test *v and decrement if it is greater than 0.
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* The function returns the old value of *v minus 1, even if
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* the atomic variable, v, was not decremented.
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*/
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static __inline__ int atomic_dec_if_positive(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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PPC_RELEASE_BARRIER
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"1: lwarx %0,0,%1 # atomic_dec_if_positive\n\
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cmpwi %0,1\n\
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addi %0,%0,-1\n\
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blt- 2f\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1\n\
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bne- 1b"
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PPC_ACQUIRE_BARRIER
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"\n\
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2:" : "=&b" (t)
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: "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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#define smp_mb__before_atomic_dec() smp_mb()
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#define smp_mb__after_atomic_dec() smp_mb()
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#define smp_mb__before_atomic_inc() smp_mb()
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#define smp_mb__after_atomic_inc() smp_mb()
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#ifdef __powerpc64__
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#define ATOMIC64_INIT(i) { (i) }
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static __inline__ long atomic64_read(const atomic64_t *v)
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{
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long t;
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__asm__ __volatile__("ld%U1%X1 %0,%1" : "=r"(t) : "m"(v->counter));
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return t;
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}
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static __inline__ void atomic64_set(atomic64_t *v, long i)
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{
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__asm__ __volatile__("std%U0%X0 %1,%0" : "=m"(v->counter) : "r"(i));
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}
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static __inline__ void atomic64_add(long a, atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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"1: ldarx %0,0,%3 # atomic64_add\n\
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add %0,%2,%0\n\
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stdcx. %0,0,%3 \n\
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bne- 1b"
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: "=&r" (t), "+m" (v->counter)
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: "r" (a), "r" (&v->counter)
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: "cc");
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}
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static __inline__ long atomic64_add_return(long a, atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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PPC_RELEASE_BARRIER
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"1: ldarx %0,0,%2 # atomic64_add_return\n\
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add %0,%1,%0\n\
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stdcx. %0,0,%2 \n\
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bne- 1b"
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PPC_ACQUIRE_BARRIER
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: "=&r" (t)
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: "r" (a), "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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#define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
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static __inline__ void atomic64_sub(long a, atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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"1: ldarx %0,0,%3 # atomic64_sub\n\
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subf %0,%2,%0\n\
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stdcx. %0,0,%3 \n\
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bne- 1b"
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: "=&r" (t), "+m" (v->counter)
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: "r" (a), "r" (&v->counter)
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: "cc");
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}
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static __inline__ long atomic64_sub_return(long a, atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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PPC_RELEASE_BARRIER
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"1: ldarx %0,0,%2 # atomic64_sub_return\n\
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subf %0,%1,%0\n\
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stdcx. %0,0,%2 \n\
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bne- 1b"
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PPC_ACQUIRE_BARRIER
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: "=&r" (t)
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: "r" (a), "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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static __inline__ void atomic64_inc(atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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"1: ldarx %0,0,%2 # atomic64_inc\n\
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addic %0,%0,1\n\
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stdcx. %0,0,%2 \n\
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bne- 1b"
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: "=&r" (t), "+m" (v->counter)
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: "r" (&v->counter)
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: "cc", "xer");
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}
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static __inline__ long atomic64_inc_return(atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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PPC_RELEASE_BARRIER
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"1: ldarx %0,0,%1 # atomic64_inc_return\n\
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addic %0,%0,1\n\
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stdcx. %0,0,%1 \n\
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bne- 1b"
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PPC_ACQUIRE_BARRIER
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: "=&r" (t)
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: "r" (&v->counter)
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: "cc", "xer", "memory");
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return t;
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}
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/*
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* atomic64_inc_and_test - increment and test
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* @v: pointer of type atomic64_t
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*
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* Atomically increments @v by 1
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* and returns true if the result is zero, or false for all
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* other cases.
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*/
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#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
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static __inline__ void atomic64_dec(atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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"1: ldarx %0,0,%2 # atomic64_dec\n\
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addic %0,%0,-1\n\
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stdcx. %0,0,%2\n\
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bne- 1b"
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: "=&r" (t), "+m" (v->counter)
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: "r" (&v->counter)
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: "cc", "xer");
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}
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static __inline__ long atomic64_dec_return(atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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PPC_RELEASE_BARRIER
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"1: ldarx %0,0,%1 # atomic64_dec_return\n\
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addic %0,%0,-1\n\
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stdcx. %0,0,%1\n\
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bne- 1b"
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PPC_ACQUIRE_BARRIER
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: "=&r" (t)
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: "r" (&v->counter)
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: "cc", "xer", "memory");
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return t;
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}
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#define atomic64_sub_and_test(a, v) (atomic64_sub_return((a), (v)) == 0)
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#define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
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/*
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* Atomically test *v and decrement if it is greater than 0.
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* The function returns the old value of *v minus 1.
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*/
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static __inline__ long atomic64_dec_if_positive(atomic64_t *v)
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{
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long t;
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__asm__ __volatile__(
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PPC_RELEASE_BARRIER
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"1: ldarx %0,0,%1 # atomic64_dec_if_positive\n\
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addic. %0,%0,-1\n\
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blt- 2f\n\
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stdcx. %0,0,%1\n\
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bne- 1b"
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PPC_ACQUIRE_BARRIER
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"\n\
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2:" : "=&r" (t)
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: "r" (&v->counter)
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: "cc", "xer", "memory");
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return t;
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}
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#define atomic64_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
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#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
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/**
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* atomic64_add_unless - add unless the number is a given value
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* @v: pointer of type atomic64_t
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* @a: the amount to add to v...
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* @u: ...unless v is equal to u.
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*
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* Atomically adds @a to @v, so long as it was not @u.
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* Returns the old value of @v.
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*/
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static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
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{
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long t;
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__asm__ __volatile__ (
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PPC_RELEASE_BARRIER
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"1: ldarx %0,0,%1 # __atomic_add_unless\n\
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cmpd 0,%0,%3 \n\
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beq- 2f \n\
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add %0,%2,%0 \n"
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" stdcx. %0,0,%1 \n\
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bne- 1b \n"
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PPC_ACQUIRE_BARRIER
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" subf %0,%2,%0 \n\
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2:"
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: "=&r" (t)
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: "r" (&v->counter), "r" (a), "r" (u)
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: "cc", "memory");
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return t != u;
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}
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#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
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#endif /* __powerpc64__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_ATOMIC_H_ */
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