forked from Minki/linux
6d7489c74a
AXS10X boards manages it's clocks using various PLLs. These PLL has same dividers and corresponding control registers mapped to different addresses. So we add one common driver for such PLLs. Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and ODIV. Output clock value is managed using these dividers. We add pre-defined tables with supported rate values and appropriate configurations of IDIV, FBDIV and ODIV for each value. As of today we add support for PLLs that generate clock for the following devices: * ARC core on AXC CPU tiles. * ARC PGU on ARC SDP Mainboard. and more to come later. By this patch we add support for two plls (arc core pll and pgu pll), so we had to use two different init types: CLK_OF_DECLARE for arc core pll and regular probing for pgu pll. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Jose Abreu <joabreu@synopsys.com> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Signed-off-by: Jose Abreu <joabreu@synopsys.com> [sboyd@codeaurora.org: Silence dubious !x & y sparse warning, make of_axs10x_pll_clk_setup() unregister clk on failure] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
29 lines
835 B
Plaintext
29 lines
835 B
Plaintext
Binding for the AXS10X Generic PLL clock
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible: should be "snps,axs10x-<name>-pll-clock"
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"snps,axs10x-arc-pll-clock"
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"snps,axs10x-pgu-pll-clock"
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- reg: should always contain 2 pairs address - length: first for PLL config
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registers and second for corresponding LOCK CGU register.
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- clocks: shall be the input parent clock phandle for the PLL.
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- #clock-cells: from common clock binding; Should always be set to 0.
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Example:
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input-clk: input-clk {
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clock-frequency = <33333333>;
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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core-clk: core-clk@80 {
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compatible = "snps,axs10x-arc-pll-clock";
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reg = <0x80 0x10>, <0x100 0x10>;
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#clock-cells = <0>;
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clocks = <&input-clk>;
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};
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