Alexey Kardashevskiy bbb845c4ba powerpc/powernv: Implement multilevel TCE tables ... TCE tables might get too big in case of 4K IOMMU pages and DDW enabled on huge guests (hundreds of GB of RAM) so the kernel might be unable to allocate contiguous chunk of physical memory to store the TCE table. To address this, POWER8 CPU (actually, IODA2) supports multi-level TCE tables, up to 5 levels which splits the table into a tree of smaller subtables. This adds multi-level TCE tables support to pnv_pci_ioda2_table_alloc_pages() and pnv_pci_ioda2_table_free_pages() helpers. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>		2015-06-11 15:16:51 +10:00
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asm	powerpc/powernv: Implement multilevel TCE tables	2015-06-11 15:16:51 +10:00
uapi/asm	powerpc/powernv: Add opal-prd channel	2015-06-05 08:32:21 +10:00