baf4326e49
Kill off interrupt_table for all of the CPU subtypes, we now default in to stepping in to do_IRQ() for _all_ IRQ exceptions and counting the spurious ones, rather than simply flipping on the ones we cared about. This and enabling the IRQ by default automatically has already uncovered a couple of bugs and IRQs that weren't being caught, as well as some that are being generated far too often (SCI Tx Data Empty, for example). The general rationale is to use a marker for interrupt exceptions, test for it in the handle_exception() path, and skip out to do_IRQ() if it's found. Everything else follows the same behaviour of finding the cached EXPEVT value in r2/r2_bank, we just rip out the INTEVT read from entry.S entirely (except for in the kGDB NMI case, which is another matter). Note that while this changes the do_IRQ() semantics regarding r4 handling, they were fundamentally broken anyways (relying entirely on r2_bank for the cached code). With this, we do the INTEVT read from do_IRQ() itself (in the CONFIG_CPU_HAS_INTEVT case), or fall back on r4 for the muxed IRQ number, which should also be closer to what SH-2 and SH-2A want anyways. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
52 lines
1.6 KiB
ArmAsm
52 lines
1.6 KiB
ArmAsm
/*
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* arch/sh/kernel/cpu/sh3/ex.S
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*
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* The SH-3 exception vector table.
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* Copyright (C) 1999, 2000, 2002 Niibe Yutaka
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* Copyright (C) 2003 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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*/
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#include <linux/linkage.h>
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.align 2
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.data
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ENTRY(exception_handling_table)
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.long exception_error /* 000 */
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.long exception_error
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#if defined(CONFIG_MMU)
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.long tlb_miss_load /* 040 */
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.long tlb_miss_store
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.long initial_page_write
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.long tlb_protection_violation_load
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.long tlb_protection_violation_store
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.long address_error_load
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.long address_error_store /* 100 */
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#else
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.long exception_error ! tlb miss load /* 040 */
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.long exception_error ! tlb miss store
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.long exception_error ! initial page write
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.long exception_error ! tlb prot violation load
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.long exception_error ! tlb prot violation store
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.long exception_error ! address error load
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.long exception_error ! address error store /* 100 */
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#endif
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.long exception_error ! fpu_exception /* 120 */
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.long exception_error /* 140 */
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.long system_call ! Unconditional Trap /* 160 */
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.long exception_error ! reserved_instruction (filled by trap_init) /* 180 */
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.long exception_error ! illegal_slot_instruction (filled by trap_init) /*1A0*/
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ENTRY(nmi_slot)
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#if defined (CONFIG_KGDB_NMI)
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.long debug_enter /* 1C0 */ ! Allow trap to debugger
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#else
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.long exception_none /* 1C0 */ ! Not implemented yet
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#endif
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ENTRY(user_break_point_trap)
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.long break_point_trap /* 1E0 */
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