forked from Minki/linux
26c0b26dcd
The files a3xx_gpu.c and a4xx_gpu.c have ifdefs for the OCMEM support that was missing upstream. Add two new functions (adreno_gpu_ocmem_init and adreno_gpu_ocmem_cleanup) that removes some duplicated code. Signed-off-by: Brian Masney <masneyb@onstation.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Tested-by: Gabriel Francisco <frc.gabrielgmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
983 lines
24 KiB
C
983 lines
24 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* Copyright (c) 2014 The Linux Foundation. All rights reserved.
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*/
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#include <linux/ascii85.h>
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#include <linux/interconnect.h>
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#include <linux/qcom_scm.h>
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#include <linux/kernel.h>
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#include <linux/of_address.h>
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#include <linux/pm_opp.h>
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#include <linux/slab.h>
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#include <linux/soc/qcom/mdt_loader.h>
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#include <soc/qcom/ocmem.h>
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#include "adreno_gpu.h"
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#include "msm_gem.h"
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#include "msm_mmu.h"
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static bool zap_available = true;
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static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname,
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u32 pasid)
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{
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struct device *dev = &gpu->pdev->dev;
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const struct firmware *fw;
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struct device_node *np, *mem_np;
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struct resource r;
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phys_addr_t mem_phys;
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ssize_t mem_size;
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void *mem_region = NULL;
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int ret;
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if (!IS_ENABLED(CONFIG_ARCH_QCOM)) {
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zap_available = false;
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return -EINVAL;
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}
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np = of_get_child_by_name(dev->of_node, "zap-shader");
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if (!np) {
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zap_available = false;
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return -ENODEV;
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}
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mem_np = of_parse_phandle(np, "memory-region", 0);
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of_node_put(np);
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if (!mem_np) {
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zap_available = false;
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return -EINVAL;
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}
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ret = of_address_to_resource(mem_np, 0, &r);
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of_node_put(mem_np);
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if (ret)
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return ret;
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mem_phys = r.start;
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/* Request the MDT file for the firmware */
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fw = adreno_request_fw(to_adreno_gpu(gpu), fwname);
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if (IS_ERR(fw)) {
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DRM_DEV_ERROR(dev, "Unable to load %s\n", fwname);
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return PTR_ERR(fw);
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}
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/* Figure out how much memory we need */
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mem_size = qcom_mdt_get_size(fw);
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if (mem_size < 0) {
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ret = mem_size;
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goto out;
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}
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if (mem_size > resource_size(&r)) {
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DRM_DEV_ERROR(dev,
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"memory region is too small to load the MDT\n");
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ret = -E2BIG;
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goto out;
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}
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/* Allocate memory for the firmware image */
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mem_region = memremap(mem_phys, mem_size, MEMREMAP_WC);
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if (!mem_region) {
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ret = -ENOMEM;
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goto out;
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}
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/*
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* Load the rest of the MDT
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*
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* Note that we could be dealing with two different paths, since
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* with upstream linux-firmware it would be in a qcom/ subdir..
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* adreno_request_fw() handles this, but qcom_mdt_load() does
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* not. But since we've already gotten through adreno_request_fw()
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* we know which of the two cases it is:
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*/
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if (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY) {
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ret = qcom_mdt_load(dev, fw, fwname, pasid,
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mem_region, mem_phys, mem_size, NULL);
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} else {
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char *newname;
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newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname);
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ret = qcom_mdt_load(dev, fw, newname, pasid,
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mem_region, mem_phys, mem_size, NULL);
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kfree(newname);
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}
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if (ret)
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goto out;
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/* Send the image to the secure world */
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ret = qcom_scm_pas_auth_and_reset(pasid);
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/*
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* If the scm call returns -EOPNOTSUPP we assume that this target
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* doesn't need/support the zap shader so quietly fail
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*/
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if (ret == -EOPNOTSUPP)
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zap_available = false;
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else if (ret)
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DRM_DEV_ERROR(dev, "Unable to authorize the image\n");
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out:
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if (mem_region)
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memunmap(mem_region);
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release_firmware(fw);
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return ret;
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}
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int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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struct platform_device *pdev = gpu->pdev;
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/* Short cut if we determine the zap shader isn't available/needed */
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if (!zap_available)
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return -ENODEV;
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/* We need SCM to be able to load the firmware */
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if (!qcom_scm_is_available()) {
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DRM_DEV_ERROR(&pdev->dev, "SCM is not available\n");
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return -EPROBE_DEFER;
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}
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/* Each GPU has a target specific zap shader firmware name to use */
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if (!adreno_gpu->info->zapfw) {
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zap_available = false;
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DRM_DEV_ERROR(&pdev->dev,
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"Zap shader firmware file not specified for this target\n");
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return -ENODEV;
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}
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return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid);
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}
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int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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switch (param) {
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case MSM_PARAM_GPU_ID:
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*value = adreno_gpu->info->revn;
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return 0;
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case MSM_PARAM_GMEM_SIZE:
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*value = adreno_gpu->gmem;
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return 0;
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case MSM_PARAM_GMEM_BASE:
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*value = 0x100000;
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return 0;
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case MSM_PARAM_CHIP_ID:
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*value = adreno_gpu->rev.patchid |
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(adreno_gpu->rev.minor << 8) |
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(adreno_gpu->rev.major << 16) |
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(adreno_gpu->rev.core << 24);
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return 0;
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case MSM_PARAM_MAX_FREQ:
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*value = adreno_gpu->base.fast_rate;
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return 0;
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case MSM_PARAM_TIMESTAMP:
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if (adreno_gpu->funcs->get_timestamp) {
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int ret;
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pm_runtime_get_sync(&gpu->pdev->dev);
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ret = adreno_gpu->funcs->get_timestamp(gpu, value);
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pm_runtime_put_autosuspend(&gpu->pdev->dev);
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return ret;
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}
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return -EINVAL;
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case MSM_PARAM_NR_RINGS:
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*value = gpu->nr_rings;
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return 0;
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case MSM_PARAM_PP_PGTABLE:
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*value = 0;
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return 0;
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case MSM_PARAM_FAULTS:
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*value = gpu->global_faults;
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return 0;
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default:
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DBG("%s: invalid param: %u", gpu->name, param);
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return -EINVAL;
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}
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}
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const struct firmware *
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adreno_request_fw(struct adreno_gpu *adreno_gpu, const char *fwname)
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{
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struct drm_device *drm = adreno_gpu->base.dev;
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const struct firmware *fw = NULL;
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char *newname;
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int ret;
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newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname);
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if (!newname)
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return ERR_PTR(-ENOMEM);
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/*
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* Try first to load from qcom/$fwfile using a direct load (to avoid
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* a potential timeout waiting for usermode helper)
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*/
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if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
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(adreno_gpu->fwloc == FW_LOCATION_NEW)) {
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ret = request_firmware_direct(&fw, newname, drm->dev);
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if (!ret) {
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DRM_DEV_INFO(drm->dev, "loaded %s from new location\n",
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newname);
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adreno_gpu->fwloc = FW_LOCATION_NEW;
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goto out;
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} else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
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DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
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newname, ret);
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fw = ERR_PTR(ret);
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goto out;
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}
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}
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/*
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* Then try the legacy location without qcom/ prefix
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*/
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if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
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(adreno_gpu->fwloc == FW_LOCATION_LEGACY)) {
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ret = request_firmware_direct(&fw, fwname, drm->dev);
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if (!ret) {
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DRM_DEV_INFO(drm->dev, "loaded %s from legacy location\n",
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newname);
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adreno_gpu->fwloc = FW_LOCATION_LEGACY;
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goto out;
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} else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
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DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
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fwname, ret);
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fw = ERR_PTR(ret);
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goto out;
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}
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}
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/*
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* Finally fall back to request_firmware() for cases where the
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* usermode helper is needed (I think mainly android)
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*/
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if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) ||
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(adreno_gpu->fwloc == FW_LOCATION_HELPER)) {
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ret = request_firmware(&fw, newname, drm->dev);
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if (!ret) {
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DRM_DEV_INFO(drm->dev, "loaded %s with helper\n",
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newname);
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adreno_gpu->fwloc = FW_LOCATION_HELPER;
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goto out;
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} else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) {
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DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n",
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newname, ret);
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fw = ERR_PTR(ret);
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goto out;
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}
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}
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DRM_DEV_ERROR(drm->dev, "failed to load %s\n", fwname);
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fw = ERR_PTR(-ENOENT);
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out:
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kfree(newname);
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return fw;
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}
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int adreno_load_fw(struct adreno_gpu *adreno_gpu)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) {
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const struct firmware *fw;
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if (!adreno_gpu->info->fw[i])
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continue;
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/* Skip if the firmware has already been loaded */
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if (adreno_gpu->fw[i])
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continue;
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fw = adreno_request_fw(adreno_gpu, adreno_gpu->info->fw[i]);
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if (IS_ERR(fw))
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return PTR_ERR(fw);
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adreno_gpu->fw[i] = fw;
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}
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return 0;
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}
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struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
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const struct firmware *fw, u64 *iova)
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{
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struct drm_gem_object *bo;
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void *ptr;
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ptr = msm_gem_kernel_new_locked(gpu->dev, fw->size - 4,
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MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova);
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if (IS_ERR(ptr))
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return ERR_CAST(ptr);
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memcpy(ptr, &fw->data[4], fw->size - 4);
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msm_gem_put_vaddr(bo);
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return bo;
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}
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int adreno_hw_init(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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int ret, i;
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DBG("%s", gpu->name);
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ret = adreno_load_fw(adreno_gpu);
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if (ret)
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return ret;
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for (i = 0; i < gpu->nr_rings; i++) {
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struct msm_ringbuffer *ring = gpu->rb[i];
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if (!ring)
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continue;
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ring->cur = ring->start;
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ring->next = ring->start;
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/* reset completed fence seqno: */
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ring->memptrs->fence = ring->seqno;
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ring->memptrs->rptr = 0;
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}
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/*
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* Setup REG_CP_RB_CNTL. The same value is used across targets (with
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* the excpetion of A430 that disables the RPTR shadow) - the cacluation
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* for the ringbuffer size and block size is moved to msm_gpu.h for the
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* pre-processor to deal with and the A430 variant is ORed in here
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*/
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adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
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MSM_GPU_RB_CNTL_DEFAULT |
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(adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0));
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/* Setup ringbuffer address - use ringbuffer[0] for GPU init */
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adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_BASE,
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REG_ADRENO_CP_RB_BASE_HI, gpu->rb[0]->iova);
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if (!adreno_is_a430(adreno_gpu)) {
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adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR,
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REG_ADRENO_CP_RB_RPTR_ADDR_HI,
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rbmemptr(gpu->rb[0], rptr));
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}
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return 0;
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}
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/* Use this helper to read rptr, since a430 doesn't update rptr in memory */
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static uint32_t get_rptr(struct adreno_gpu *adreno_gpu,
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struct msm_ringbuffer *ring)
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{
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if (adreno_is_a430(adreno_gpu))
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return ring->memptrs->rptr = adreno_gpu_read(
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adreno_gpu, REG_ADRENO_CP_RB_RPTR);
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else
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return ring->memptrs->rptr;
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}
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struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu)
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{
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return gpu->rb[0];
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}
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void adreno_recover(struct msm_gpu *gpu)
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{
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struct drm_device *dev = gpu->dev;
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int ret;
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// XXX pm-runtime?? we *need* the device to be off after this
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// so maybe continuing to call ->pm_suspend/resume() is better?
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gpu->funcs->pm_suspend(gpu);
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gpu->funcs->pm_resume(gpu);
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ret = msm_gpu_hw_init(gpu);
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if (ret) {
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DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);
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/* hmm, oh well? */
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}
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}
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void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
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struct msm_file_private *ctx)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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struct msm_drm_private *priv = gpu->dev->dev_private;
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struct msm_ringbuffer *ring = submit->ring;
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unsigned i;
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for (i = 0; i < submit->nr_cmds; i++) {
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switch (submit->cmd[i].type) {
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case MSM_SUBMIT_CMD_IB_TARGET_BUF:
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/* ignore IB-targets */
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break;
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case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
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/* ignore if there has not been a ctx switch: */
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if (priv->lastctx == ctx)
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break;
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/* fall-thru */
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case MSM_SUBMIT_CMD_BUF:
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OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ?
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CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
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OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
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OUT_RING(ring, submit->cmd[i].size);
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OUT_PKT2(ring);
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break;
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}
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}
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OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);
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OUT_RING(ring, submit->seqno);
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if (adreno_is_a3xx(adreno_gpu) || adreno_is_a4xx(adreno_gpu)) {
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/* Flush HLSQ lazy updates to make sure there is nothing
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* pending for indirect loads after the timestamp has
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* passed:
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*/
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OUT_PKT3(ring, CP_EVENT_WRITE, 1);
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OUT_RING(ring, HLSQ_FLUSH);
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}
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/* wait for idle before cache flush/interrupt */
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OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
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OUT_RING(ring, 0x00000000);
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if (!adreno_is_a2xx(adreno_gpu)) {
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/* BIT(31) of CACHE_FLUSH_TS triggers CACHE_FLUSH_TS IRQ from GPU */
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OUT_PKT3(ring, CP_EVENT_WRITE, 3);
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OUT_RING(ring, CACHE_FLUSH_TS | BIT(31));
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OUT_RING(ring, rbmemptr(ring, fence));
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OUT_RING(ring, submit->seqno);
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} else {
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/* BIT(31) means something else on a2xx */
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OUT_PKT3(ring, CP_EVENT_WRITE, 3);
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OUT_RING(ring, CACHE_FLUSH_TS);
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OUT_RING(ring, rbmemptr(ring, fence));
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OUT_RING(ring, submit->seqno);
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OUT_PKT3(ring, CP_INTERRUPT, 1);
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OUT_RING(ring, 0x80000000);
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}
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#if 0
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if (adreno_is_a3xx(adreno_gpu)) {
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/* Dummy set-constant to trigger context rollover */
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG));
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OUT_RING(ring, 0x00000000);
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}
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#endif
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gpu->funcs->flush(gpu, ring);
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}
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void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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|
uint32_t wptr;
|
|
|
|
/* Copy the shadow to the actual register */
|
|
ring->cur = ring->next;
|
|
|
|
/*
|
|
* Mask wptr value that we calculate to fit in the HW range. This is
|
|
* to account for the possibility that the last command fit exactly into
|
|
* the ringbuffer and rb->next hasn't wrapped to zero yet
|
|
*/
|
|
wptr = get_wptr(ring);
|
|
|
|
/* ensure writes to ringbuffer have hit system memory: */
|
|
mb();
|
|
|
|
adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr);
|
|
}
|
|
|
|
bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
|
|
{
|
|
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
|
uint32_t wptr = get_wptr(ring);
|
|
|
|
/* wait for CP to drain ringbuffer: */
|
|
if (!spin_until(get_rptr(adreno_gpu, ring) == wptr))
|
|
return true;
|
|
|
|
/* TODO maybe we need to reset GPU here to recover from hang? */
|
|
DRM_ERROR("%s: timeout waiting to drain ringbuffer %d rptr/wptr = %X/%X\n",
|
|
gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr);
|
|
|
|
return false;
|
|
}
|
|
|
|
int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state)
|
|
{
|
|
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
|
int i, count = 0;
|
|
|
|
kref_init(&state->ref);
|
|
|
|
ktime_get_real_ts64(&state->time);
|
|
|
|
for (i = 0; i < gpu->nr_rings; i++) {
|
|
int size = 0, j;
|
|
|
|
state->ring[i].fence = gpu->rb[i]->memptrs->fence;
|
|
state->ring[i].iova = gpu->rb[i]->iova;
|
|
state->ring[i].seqno = gpu->rb[i]->seqno;
|
|
state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]);
|
|
state->ring[i].wptr = get_wptr(gpu->rb[i]);
|
|
|
|
/* Copy at least 'wptr' dwords of the data */
|
|
size = state->ring[i].wptr;
|
|
|
|
/* After wptr find the last non zero dword to save space */
|
|
for (j = state->ring[i].wptr; j < MSM_GPU_RINGBUFFER_SZ >> 2; j++)
|
|
if (gpu->rb[i]->start[j])
|
|
size = j + 1;
|
|
|
|
if (size) {
|
|
state->ring[i].data = kvmalloc(size << 2, GFP_KERNEL);
|
|
if (state->ring[i].data) {
|
|
memcpy(state->ring[i].data, gpu->rb[i]->start, size << 2);
|
|
state->ring[i].data_size = size << 2;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Some targets prefer to collect their own registers */
|
|
if (!adreno_gpu->registers)
|
|
return 0;
|
|
|
|
/* Count the number of registers */
|
|
for (i = 0; adreno_gpu->registers[i] != ~0; i += 2)
|
|
count += adreno_gpu->registers[i + 1] -
|
|
adreno_gpu->registers[i] + 1;
|
|
|
|
state->registers = kcalloc(count * 2, sizeof(u32), GFP_KERNEL);
|
|
if (state->registers) {
|
|
int pos = 0;
|
|
|
|
for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
|
|
u32 start = adreno_gpu->registers[i];
|
|
u32 end = adreno_gpu->registers[i + 1];
|
|
u32 addr;
|
|
|
|
for (addr = start; addr <= end; addr++) {
|
|
state->registers[pos++] = addr;
|
|
state->registers[pos++] = gpu_read(gpu, addr);
|
|
}
|
|
}
|
|
|
|
state->nr_registers = count;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void adreno_gpu_state_destroy(struct msm_gpu_state *state)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(state->ring); i++)
|
|
kvfree(state->ring[i].data);
|
|
|
|
for (i = 0; state->bos && i < state->nr_bos; i++)
|
|
kvfree(state->bos[i].data);
|
|
|
|
kfree(state->bos);
|
|
kfree(state->comm);
|
|
kfree(state->cmd);
|
|
kfree(state->registers);
|
|
}
|
|
|
|
static void adreno_gpu_state_kref_destroy(struct kref *kref)
|
|
{
|
|
struct msm_gpu_state *state = container_of(kref,
|
|
struct msm_gpu_state, ref);
|
|
|
|
adreno_gpu_state_destroy(state);
|
|
kfree(state);
|
|
}
|
|
|
|
int adreno_gpu_state_put(struct msm_gpu_state *state)
|
|
{
|
|
if (IS_ERR_OR_NULL(state))
|
|
return 1;
|
|
|
|
return kref_put(&state->ref, adreno_gpu_state_kref_destroy);
|
|
}
|
|
|
|
#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
|
|
|
|
static char *adreno_gpu_ascii85_encode(u32 *src, size_t len)
|
|
{
|
|
void *buf;
|
|
size_t buf_itr = 0, buffer_size;
|
|
char out[ASCII85_BUFSZ];
|
|
long l;
|
|
int i;
|
|
|
|
if (!src || !len)
|
|
return NULL;
|
|
|
|
l = ascii85_encode_len(len);
|
|
|
|
/*
|
|
* Ascii85 outputs either a 5 byte string or a 1 byte string. So we
|
|
* account for the worst case of 5 bytes per dword plus the 1 for '\0'
|
|
*/
|
|
buffer_size = (l * 5) + 1;
|
|
|
|
buf = kvmalloc(buffer_size, GFP_KERNEL);
|
|
if (!buf)
|
|
return NULL;
|
|
|
|
for (i = 0; i < l; i++)
|
|
buf_itr += snprintf(buf + buf_itr, buffer_size - buf_itr, "%s",
|
|
ascii85_encode(src[i], out));
|
|
|
|
return buf;
|
|
}
|
|
|
|
/* len is expected to be in bytes */
|
|
static void adreno_show_object(struct drm_printer *p, void **ptr, int len,
|
|
bool *encoded)
|
|
{
|
|
if (!*ptr || !len)
|
|
return;
|
|
|
|
if (!*encoded) {
|
|
long datalen, i;
|
|
u32 *buf = *ptr;
|
|
|
|
/*
|
|
* Only dump the non-zero part of the buffer - rarely will
|
|
* any data completely fill the entire allocated size of
|
|
* the buffer.
|
|
*/
|
|
for (datalen = 0, i = 0; i < len >> 2; i++)
|
|
if (buf[i])
|
|
datalen = ((i + 1) << 2);
|
|
|
|
/*
|
|
* If we reach here, then the originally captured binary buffer
|
|
* will be replaced with the ascii85 encoded string
|
|
*/
|
|
*ptr = adreno_gpu_ascii85_encode(buf, datalen);
|
|
|
|
kvfree(buf);
|
|
|
|
*encoded = true;
|
|
}
|
|
|
|
if (!*ptr)
|
|
return;
|
|
|
|
drm_puts(p, " data: !!ascii85 |\n");
|
|
drm_puts(p, " ");
|
|
|
|
drm_puts(p, *ptr);
|
|
|
|
drm_puts(p, "\n");
|
|
}
|
|
|
|
void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
|
|
struct drm_printer *p)
|
|
{
|
|
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
|
int i;
|
|
|
|
if (IS_ERR_OR_NULL(state))
|
|
return;
|
|
|
|
drm_printf(p, "revision: %d (%d.%d.%d.%d)\n",
|
|
adreno_gpu->info->revn, adreno_gpu->rev.core,
|
|
adreno_gpu->rev.major, adreno_gpu->rev.minor,
|
|
adreno_gpu->rev.patchid);
|
|
|
|
drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status);
|
|
|
|
drm_puts(p, "ringbuffer:\n");
|
|
|
|
for (i = 0; i < gpu->nr_rings; i++) {
|
|
drm_printf(p, " - id: %d\n", i);
|
|
drm_printf(p, " iova: 0x%016llx\n", state->ring[i].iova);
|
|
drm_printf(p, " last-fence: %d\n", state->ring[i].seqno);
|
|
drm_printf(p, " retired-fence: %d\n", state->ring[i].fence);
|
|
drm_printf(p, " rptr: %d\n", state->ring[i].rptr);
|
|
drm_printf(p, " wptr: %d\n", state->ring[i].wptr);
|
|
drm_printf(p, " size: %d\n", MSM_GPU_RINGBUFFER_SZ);
|
|
|
|
adreno_show_object(p, &state->ring[i].data,
|
|
state->ring[i].data_size, &state->ring[i].encoded);
|
|
}
|
|
|
|
if (state->bos) {
|
|
drm_puts(p, "bos:\n");
|
|
|
|
for (i = 0; i < state->nr_bos; i++) {
|
|
drm_printf(p, " - iova: 0x%016llx\n",
|
|
state->bos[i].iova);
|
|
drm_printf(p, " size: %zd\n", state->bos[i].size);
|
|
|
|
adreno_show_object(p, &state->bos[i].data,
|
|
state->bos[i].size, &state->bos[i].encoded);
|
|
}
|
|
}
|
|
|
|
if (state->nr_registers) {
|
|
drm_puts(p, "registers:\n");
|
|
|
|
for (i = 0; i < state->nr_registers; i++) {
|
|
drm_printf(p, " - { offset: 0x%04x, value: 0x%08x }\n",
|
|
state->registers[i * 2] << 2,
|
|
state->registers[(i * 2) + 1]);
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/* Dump common gpu status and scratch registers on any hang, to make
|
|
* the hangcheck logs more useful. The scratch registers seem always
|
|
* safe to read when GPU has hung (unlike some other regs, depending
|
|
* on how the GPU hung), and they are useful to match up to cmdstream
|
|
* dumps when debugging hangs:
|
|
*/
|
|
void adreno_dump_info(struct msm_gpu *gpu)
|
|
{
|
|
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
|
int i;
|
|
|
|
printk("revision: %d (%d.%d.%d.%d)\n",
|
|
adreno_gpu->info->revn, adreno_gpu->rev.core,
|
|
adreno_gpu->rev.major, adreno_gpu->rev.minor,
|
|
adreno_gpu->rev.patchid);
|
|
|
|
for (i = 0; i < gpu->nr_rings; i++) {
|
|
struct msm_ringbuffer *ring = gpu->rb[i];
|
|
|
|
printk("rb %d: fence: %d/%d\n", i,
|
|
ring->memptrs->fence,
|
|
ring->seqno);
|
|
|
|
printk("rptr: %d\n", get_rptr(adreno_gpu, ring));
|
|
printk("rb wptr: %d\n", get_wptr(ring));
|
|
}
|
|
}
|
|
|
|
/* would be nice to not have to duplicate the _show() stuff with printk(): */
|
|
void adreno_dump(struct msm_gpu *gpu)
|
|
{
|
|
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
|
int i;
|
|
|
|
if (!adreno_gpu->registers)
|
|
return;
|
|
|
|
/* dump these out in a form that can be parsed by demsm: */
|
|
printk("IO:region %s 00000000 00020000\n", gpu->name);
|
|
for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
|
|
uint32_t start = adreno_gpu->registers[i];
|
|
uint32_t end = adreno_gpu->registers[i+1];
|
|
uint32_t addr;
|
|
|
|
for (addr = start; addr <= end; addr++) {
|
|
uint32_t val = gpu_read(gpu, addr);
|
|
printk("IO:R %08x %08x\n", addr<<2, val);
|
|
}
|
|
}
|
|
}
|
|
|
|
static uint32_t ring_freewords(struct msm_ringbuffer *ring)
|
|
{
|
|
struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu);
|
|
uint32_t size = MSM_GPU_RINGBUFFER_SZ >> 2;
|
|
/* Use ring->next to calculate free size */
|
|
uint32_t wptr = ring->next - ring->start;
|
|
uint32_t rptr = get_rptr(adreno_gpu, ring);
|
|
return (rptr + (size - 1) - wptr) % size;
|
|
}
|
|
|
|
void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords)
|
|
{
|
|
if (spin_until(ring_freewords(ring) >= ndwords))
|
|
DRM_DEV_ERROR(ring->gpu->dev->dev,
|
|
"timeout waiting for space in ringbuffer %d\n",
|
|
ring->id);
|
|
}
|
|
|
|
/* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */
|
|
static int adreno_get_legacy_pwrlevels(struct device *dev)
|
|
{
|
|
struct device_node *child, *node;
|
|
int ret;
|
|
|
|
node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels");
|
|
if (!node) {
|
|
DRM_DEV_ERROR(dev, "Could not find the GPU powerlevels\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
for_each_child_of_node(node, child) {
|
|
unsigned int val;
|
|
|
|
ret = of_property_read_u32(child, "qcom,gpu-freq", &val);
|
|
if (ret)
|
|
continue;
|
|
|
|
/*
|
|
* Skip the intentionally bogus clock value found at the bottom
|
|
* of most legacy frequency tables
|
|
*/
|
|
if (val != 27000000)
|
|
dev_pm_opp_add(dev, val, 0);
|
|
}
|
|
|
|
of_node_put(node);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int adreno_get_pwrlevels(struct device *dev,
|
|
struct msm_gpu *gpu)
|
|
{
|
|
unsigned long freq = ULONG_MAX;
|
|
struct dev_pm_opp *opp;
|
|
int ret;
|
|
|
|
gpu->fast_rate = 0;
|
|
|
|
/* You down with OPP? */
|
|
if (!of_find_property(dev->of_node, "operating-points-v2", NULL))
|
|
ret = adreno_get_legacy_pwrlevels(dev);
|
|
else {
|
|
ret = dev_pm_opp_of_add_table(dev);
|
|
if (ret)
|
|
DRM_DEV_ERROR(dev, "Unable to set the OPP table\n");
|
|
}
|
|
|
|
if (!ret) {
|
|
/* Find the fastest defined rate */
|
|
opp = dev_pm_opp_find_freq_floor(dev, &freq);
|
|
if (!IS_ERR(opp)) {
|
|
gpu->fast_rate = freq;
|
|
dev_pm_opp_put(opp);
|
|
}
|
|
}
|
|
|
|
if (!gpu->fast_rate) {
|
|
dev_warn(dev,
|
|
"Could not find a clock rate. Using a reasonable default\n");
|
|
/* Pick a suitably safe clock speed for any target */
|
|
gpu->fast_rate = 200000000;
|
|
}
|
|
|
|
DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate);
|
|
|
|
/* Check for an interconnect path for the bus */
|
|
gpu->icc_path = of_icc_get(dev, NULL);
|
|
if (IS_ERR(gpu->icc_path))
|
|
gpu->icc_path = NULL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
|
|
struct adreno_ocmem *adreno_ocmem)
|
|
{
|
|
struct ocmem_buf *ocmem_hdl;
|
|
struct ocmem *ocmem;
|
|
|
|
ocmem = of_get_ocmem(dev);
|
|
if (IS_ERR(ocmem)) {
|
|
if (PTR_ERR(ocmem) == -ENODEV) {
|
|
/*
|
|
* Return success since either the ocmem property was
|
|
* not specified in device tree, or ocmem support is
|
|
* not compiled into the kernel.
|
|
*/
|
|
return 0;
|
|
}
|
|
|
|
return PTR_ERR(ocmem);
|
|
}
|
|
|
|
ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->gmem);
|
|
if (IS_ERR(ocmem_hdl))
|
|
return PTR_ERR(ocmem_hdl);
|
|
|
|
adreno_ocmem->ocmem = ocmem;
|
|
adreno_ocmem->base = ocmem_hdl->addr;
|
|
adreno_ocmem->hdl = ocmem_hdl;
|
|
adreno_gpu->gmem = ocmem_hdl->len;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem)
|
|
{
|
|
if (adreno_ocmem && adreno_ocmem->base)
|
|
ocmem_free(adreno_ocmem->ocmem, OCMEM_GRAPHICS,
|
|
adreno_ocmem->hdl);
|
|
}
|
|
|
|
int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
|
|
struct adreno_gpu *adreno_gpu,
|
|
const struct adreno_gpu_funcs *funcs, int nr_rings)
|
|
{
|
|
struct adreno_platform_config *config = pdev->dev.platform_data;
|
|
struct msm_gpu_config adreno_gpu_config = { 0 };
|
|
struct msm_gpu *gpu = &adreno_gpu->base;
|
|
|
|
adreno_gpu->funcs = funcs;
|
|
adreno_gpu->info = adreno_info(config->rev);
|
|
adreno_gpu->gmem = adreno_gpu->info->gmem;
|
|
adreno_gpu->revn = adreno_gpu->info->revn;
|
|
adreno_gpu->rev = config->rev;
|
|
|
|
adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
|
|
|
|
adreno_gpu_config.va_start = SZ_16M;
|
|
adreno_gpu_config.va_end = 0xffffffff;
|
|
/* maximum range of a2xx mmu */
|
|
if (adreno_is_a2xx(adreno_gpu))
|
|
adreno_gpu_config.va_end = SZ_16M + 0xfff * SZ_64K;
|
|
|
|
adreno_gpu_config.nr_rings = nr_rings;
|
|
|
|
adreno_get_pwrlevels(&pdev->dev, gpu);
|
|
|
|
pm_runtime_set_autosuspend_delay(&pdev->dev,
|
|
adreno_gpu->info->inactive_period);
|
|
pm_runtime_use_autosuspend(&pdev->dev);
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
|
|
adreno_gpu->info->name, &adreno_gpu_config);
|
|
}
|
|
|
|
void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu)
|
|
{
|
|
struct msm_gpu *gpu = &adreno_gpu->base;
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++)
|
|
release_firmware(adreno_gpu->fw[i]);
|
|
|
|
icc_put(gpu->icc_path);
|
|
|
|
msm_gpu_cleanup(&adreno_gpu->base);
|
|
}
|