8872fc22c2
DT files to enable cygnus consisting on reference designs and cygnus core configuration. Reviewed-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Arun Parameswaran <aparames@broadcom.com> Tested-by: Jonathan Richardson <jonathar@broadcom.com> Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com> Signed-off-by: Scott Branden <sbranden@broadcom.com>
101 lines
2.4 KiB
Plaintext
101 lines
2.4 KiB
Plaintext
/*
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* Copyright 2014 Broadcom Corporation. All rights reserved.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "brcm,cygnus";
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model = "Broadcom Cygnus SoC";
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x0>;
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};
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};
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/include/ "bcm-cygnus-clock.dtsi"
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amba {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "arm,amba-bus", "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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wdt@18009000 {
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compatible = "arm,sp805" , "arm,primecell";
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reg = <0x18009000 0x1000>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&axi81_clk>;
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clock-names = "apb_pclk";
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};
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};
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uart3: serial@18023000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x18023000 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <100000000>;
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clocks = <&axi81_clk>;
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status = "okay";
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};
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uart0: serial@18020000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x18020000 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&axi81_clk>;
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clock-frequency = <100000000>;
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status = "okay";
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};
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gic: interrupt-controller@19021000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x19021000 0x1000>,
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<0x19020100 0x100>;
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};
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L2: l2-cache {
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compatible = "arm,pl310-cache";
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reg = <0x19022000 0x1000>;
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cache-unified;
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cache-level = <2>;
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};
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timer@19020200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x19020200 0x100>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&periph_clk>;
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};
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};
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