forked from Minki/linux
3060e9f0d1
The ARM architecture defines the memory locations that are permitted
to be accessed as the result of a speculative instruction fetch from
an exception level for which all stages of translation are disabled.
Specifically, the core is permitted to speculatively fetch from the
4KB region containing the current program counter 4K and next 4K.
When translation is changed from enabled to disabled for the running
exception level (SCTLR_ELn[M] changed from a value of 1 to 0), the
Falkor core may errantly speculatively access memory locations outside
of the 4KB region permitted by the architecture. The errant memory
access may lead to one of the following unexpected behaviors.
1) A System Error Interrupt (SEI) being raised by the Falkor core due
to the errant memory access attempting to access a region of memory
that is protected by a slave-side memory protection unit.
2) Unpredictable device behavior due to a speculative read from device
memory. This behavior may only occur if the instruction cache is
disabled prior to or coincident with translation being changed from
enabled to disabled.
The conditions leading to this erratum will not occur when either of the
following occur:
1) A higher exception level disables translation of a lower exception level
(e.g. EL2 changing SCTLR_EL1[M] from a value of 1 to 0).
2) An exception level disabling its stage-1 translation if its stage-2
translation is enabled (e.g. EL1 changing SCTLR_EL1[M] from a value of 1
to 0 when HCR_EL2[VM] has a value of 1).
To avoid the errant behavior, software must execute an ISB immediately
prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0.
Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
125 lines
2.9 KiB
ArmAsm
125 lines
2.9 KiB
ArmAsm
/*
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* EFI entry point.
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*
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* Copyright (C) 2013, 2014 Red Hat, Inc.
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* Author: Mark Salter <msalter@redhat.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#define EFI_LOAD_ERROR 0x8000000000000001
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__INIT
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/*
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* We arrive here from the EFI boot manager with:
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*
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* * CPU in little-endian mode
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* * MMU on with identity-mapped RAM
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* * Icache and Dcache on
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*
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* We will most likely be running from some place other than where
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* we want to be. The kernel image wants to be placed at TEXT_OFFSET
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* from start of RAM.
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*/
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ENTRY(entry)
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/*
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* Create a stack frame to save FP/LR with extra space
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* for image_addr variable passed to efi_entry().
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*/
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stp x29, x30, [sp, #-32]!
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mov x29, sp
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/*
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* Call efi_entry to do the real work.
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* x0 and x1 are already set up by firmware. Current runtime
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* address of image is calculated and passed via *image_addr.
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*
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* unsigned long efi_entry(void *handle,
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* efi_system_table_t *sys_table,
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* unsigned long *image_addr) ;
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*/
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adr_l x8, _text
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add x2, sp, 16
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str x8, [x2]
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bl efi_entry
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cmn x0, #1
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b.eq efi_load_fail
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/*
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* efi_entry() will have copied the kernel image if necessary and we
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* return here with device tree address in x0 and the kernel entry
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* point stored at *image_addr. Save those values in registers which
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* are callee preserved.
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*/
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mov x20, x0 // DTB address
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ldr x0, [sp, #16] // relocated _text address
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ldr w21, =stext_offset
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add x21, x0, x21
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/*
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* Calculate size of the kernel Image (same for original and copy).
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*/
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adr_l x1, _text
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adr_l x2, _edata
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sub x1, x2, x1
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/*
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* Flush the copied Image to the PoC, and ensure it is not shadowed by
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* stale icache entries from before relocation.
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*/
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bl __flush_dcache_area
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ic ialluis
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/*
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* Ensure that the rest of this function (in the original Image) is
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* visible when the caches are disabled. The I-cache can't have stale
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* entries for the VA range of the current image, so no maintenance is
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* necessary.
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*/
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adr x0, entry
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adr x1, entry_end
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sub x1, x1, x0
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bl __flush_dcache_area
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/* Turn off Dcache and MMU */
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mrs x0, CurrentEL
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cmp x0, #CurrentEL_EL2
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b.ne 1f
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mrs x0, sctlr_el2
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bic x0, x0, #1 << 0 // clear SCTLR.M
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bic x0, x0, #1 << 2 // clear SCTLR.C
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pre_disable_mmu_workaround
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msr sctlr_el2, x0
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isb
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b 2f
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1:
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mrs x0, sctlr_el1
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bic x0, x0, #1 << 0 // clear SCTLR.M
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bic x0, x0, #1 << 2 // clear SCTLR.C
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pre_disable_mmu_workaround
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msr sctlr_el1, x0
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isb
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2:
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/* Jump to kernel entry point */
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mov x0, x20
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mov x1, xzr
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mov x2, xzr
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mov x3, xzr
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br x21
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efi_load_fail:
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mov x0, #EFI_LOAD_ERROR
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ldp x29, x30, [sp], #32
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ret
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entry_end:
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ENDPROC(entry)
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