f9cb8d8d83
For DSI cmd-mode and writeback, we need to write the CTL's START register to kick things off, but we only want to do that once both the encoder and the crtc have a chance to write their corresponding flush bits. The difficulty is that when there is a full modeset (ie. encoder state has changed) we want to defer the start until encoder->enable(). But if only plane's have changed, we want to do this from crtc->commit(). The start_mask was a previous attempt to handle this, but it didn't really do the right thing since atomic conversion. Instead track in the crtc state that the start should be deferred, set to try from encoder's (or in future writeback's) atomic_check(). This way the state is part of the atomic state, and rollback can work properly if an atomic test fails. Signed-off-by: Rob Clark <robdclark@gmail.com>
87 lines
3.0 KiB
C
87 lines
3.0 KiB
C
/*
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* Copyright (c) 2014 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MDP5_CTL_H__
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#define __MDP5_CTL_H__
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#include "msm_drv.h"
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/*
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* CTL Manager prototypes:
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* mdp5_ctlm_init() returns a ctlm (CTL Manager) handler,
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* which is then used to call the other mdp5_ctlm_*(ctlm, ...) functions.
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*/
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struct mdp5_ctl_manager;
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struct mdp5_ctl_manager *mdp5_ctlm_init(struct drm_device *dev,
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void __iomem *mmio_base, struct mdp5_cfg_handler *cfg_hnd);
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void mdp5_ctlm_hw_reset(struct mdp5_ctl_manager *ctlm);
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void mdp5_ctlm_destroy(struct mdp5_ctl_manager *ctlm);
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/*
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* CTL prototypes:
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* mdp5_ctl_request(ctlm, ...) returns a ctl (CTL resource) handler,
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* which is then used to call the other mdp5_ctl_*(ctl, ...) functions.
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*/
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struct mdp5_ctl *mdp5_ctlm_request(struct mdp5_ctl_manager *ctlm, int intf_num);
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int mdp5_ctl_get_ctl_id(struct mdp5_ctl *ctl);
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struct mdp5_interface;
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struct mdp5_pipeline;
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int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_pipeline *p);
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int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl, struct mdp5_pipeline *p,
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bool enabled);
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int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
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int cursor_id, bool enable);
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int mdp5_ctl_pair(struct mdp5_ctl *ctlx, struct mdp5_ctl *ctly, bool enable);
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#define MAX_PIPE_STAGE 2
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/*
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* mdp5_ctl_blend() - Blend multiple layers on a Layer Mixer (LM)
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*
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* @stage: array to contain the pipe num for each stage
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* @stage_cnt: valid stage number in stage array
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* @ctl_blend_op_flags: blender operation mode flags
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*
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* Note:
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* CTL registers need to be flushed after calling this function
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* (call mdp5_ctl_commit() with mdp_ctl_flush_mask_ctl() mask)
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*/
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#define MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT BIT(0)
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int mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
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enum mdp5_pipe stage[][MAX_PIPE_STAGE],
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enum mdp5_pipe r_stage[][MAX_PIPE_STAGE],
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u32 stage_cnt, u32 ctl_blend_op_flags);
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/**
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* mdp_ctl_flush_mask...() - Register FLUSH masks
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*
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* These masks are used to specify which block(s) need to be flushed
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* through @flush_mask parameter in mdp5_ctl_commit(.., flush_mask).
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*/
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u32 mdp_ctl_flush_mask_lm(int lm);
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u32 mdp_ctl_flush_mask_pipe(enum mdp5_pipe pipe);
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u32 mdp_ctl_flush_mask_cursor(int cursor_id);
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u32 mdp_ctl_flush_mask_encoder(struct mdp5_interface *intf);
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/* @flush_mask: see CTL flush masks definitions below */
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u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
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u32 flush_mask, bool start);
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u32 mdp5_ctl_get_commit_status(struct mdp5_ctl *ctl);
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#endif /* __MDP5_CTL_H__ */
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