b93b2abce4
All Octeon chips can support more than 4GB of RAM. Also due to how Octeon PCI is setup, even some configurations with less than 4GB of RAM will have portions that are not accessible from 32-bit devices. Enable the swiotlb code to handle the cases where a device cannot directly do DMA. This is a complete rewrite of the Octeon DMA mapping code. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1639/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
102 lines
2.9 KiB
Plaintext
102 lines
2.9 KiB
Plaintext
config CAVIUM_OCTEON_SPECIFIC_OPTIONS
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bool "Enable Octeon specific options"
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depends on CPU_CAVIUM_OCTEON
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default "y"
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config CAVIUM_OCTEON_2ND_KERNEL
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bool "Build the kernel to be used as a 2nd kernel on the same chip"
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depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
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default "n"
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help
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This option configures this kernel to be linked at a different
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address and use the 2nd uart for output. This allows a kernel built
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with this option to be run at the same time as one built without this
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option.
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config CAVIUM_OCTEON_HW_FIX_UNALIGNED
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bool "Enable hardware fixups of unaligned loads and stores"
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depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
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default "y"
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help
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Configure the Octeon hardware to automatically fix unaligned loads
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and stores. Normally unaligned accesses are fixed using a kernel
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exception handler. This option enables the hardware automatic fixups,
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which requires only an extra 3 cycles. Disable this option if you
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are running code that relies on address exceptions on unaligned
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accesses.
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config CAVIUM_OCTEON_CVMSEG_SIZE
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int "Number of L1 cache lines reserved for CVMSEG memory"
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depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
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range 0 54
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default 1
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help
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CVMSEG LM is a segment that accesses portions of the dcache as a
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local memory; the larger CVMSEG is, the smaller the cache is.
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This selects the size of CVMSEG LM, which is in cache blocks. The
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legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
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between zero and 6192 bytes).
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config CAVIUM_OCTEON_LOCK_L2
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bool "Lock often used kernel code in the L2"
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depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
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default "y"
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help
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Enable locking parts of the kernel into the L2 cache.
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config CAVIUM_OCTEON_LOCK_L2_TLB
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bool "Lock the TLB handler in L2"
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depends on CAVIUM_OCTEON_LOCK_L2
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default "y"
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help
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Lock the low level TLB fast path into L2.
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config CAVIUM_OCTEON_LOCK_L2_EXCEPTION
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bool "Lock the exception handler in L2"
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depends on CAVIUM_OCTEON_LOCK_L2
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default "y"
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help
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Lock the low level exception handler into L2.
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config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
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bool "Lock the interrupt handler in L2"
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depends on CAVIUM_OCTEON_LOCK_L2
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default "y"
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help
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Lock the low level interrupt handler into L2.
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config CAVIUM_OCTEON_LOCK_L2_INTERRUPT
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bool "Lock the 2nd level interrupt handler in L2"
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depends on CAVIUM_OCTEON_LOCK_L2
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default "y"
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help
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Lock the 2nd level interrupt handler in L2.
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config CAVIUM_OCTEON_LOCK_L2_MEMCPY
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bool "Lock memcpy() in L2"
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depends on CAVIUM_OCTEON_LOCK_L2
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default "y"
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help
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Lock the kernel's implementation of memcpy() into L2.
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config ARCH_SPARSEMEM_ENABLE
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def_bool y
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select SPARSEMEM_STATIC
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depends on CPU_CAVIUM_OCTEON
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config CAVIUM_OCTEON_HELPER
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def_bool y
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depends on OCTEON_ETHERNET || PCI
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config IOMMU_HELPER
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bool
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config NEED_SG_DMA_LENGTH
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bool
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config SWIOTLB
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def_bool y
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depends on CPU_CAVIUM_OCTEON
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select IOMMU_HELPER
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select NEED_SG_DMA_LENGTH
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