forked from Minki/linux
600 lines
14 KiB
C
600 lines
14 KiB
C
/*
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* omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
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*
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* Copyright (C) 2009-2011 Nokia Corporation
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* Copyright (C) 2012 Texas Instruments, Inc.
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* XXX handle crossbar/shared link difference for L3?
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* XXX these should be marked initdata for multi-OMAP kernels
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*/
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#include <plat/omap_hwmod.h>
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#include <mach/irqs.h>
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#include <plat/cpu.h>
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#include <plat/dma.h>
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#include <plat/serial.h>
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#include <plat/i2c.h>
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#include <plat/gpio.h>
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#include <plat/mcspi.h>
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#include <plat/dmtimer.h>
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#include <plat/l3_2xxx.h>
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#include <plat/l4_2xxx.h>
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#include <plat/mmc.h>
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#include "omap_hwmod_common_data.h"
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#include "cm-regbits-24xx.h"
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#include "prm-regbits-24xx.h"
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#include "wd_timer.h"
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/*
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* OMAP2420 hardware module integration data
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*
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* All of the data in this section should be autogeneratable from the
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* TI hardware database or other technical documentation. Data that
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* is driver-specific or driver-kernel integration-specific belongs
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* elsewhere.
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*/
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/*
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* IP blocks
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*/
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/* IVA1 (IVA1) */
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static struct omap_hwmod_class iva1_hwmod_class = {
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.name = "iva1",
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};
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static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
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{ .name = "iva", .rst_shift = 8 },
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};
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static struct omap_hwmod omap2420_iva_hwmod = {
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.name = "iva",
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.class = &iva1_hwmod_class,
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.clkdm_name = "iva1_clkdm",
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.rst_lines = omap2420_iva_resets,
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.rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
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.main_clk = "iva1_ifck",
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};
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/* DSP */
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static struct omap_hwmod_class dsp_hwmod_class = {
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.name = "dsp",
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};
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static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
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{ .name = "logic", .rst_shift = 0 },
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{ .name = "mmu", .rst_shift = 1 },
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};
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static struct omap_hwmod omap2420_dsp_hwmod = {
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.name = "dsp",
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.class = &dsp_hwmod_class,
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.clkdm_name = "dsp_clkdm",
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.rst_lines = omap2420_dsp_resets,
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.rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
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.main_clk = "dsp_fck",
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};
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/* I2C common */
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static struct omap_hwmod_class_sysconfig i2c_sysc = {
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.rev_offs = 0x00,
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.sysc_offs = 0x20,
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.syss_offs = 0x10,
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.sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class i2c_class = {
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.name = "i2c",
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.sysc = &i2c_sysc,
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.rev = OMAP_I2C_IP_VERSION_1,
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.reset = &omap_i2c_reset,
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};
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static struct omap_i2c_dev_attr i2c_dev_attr = {
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.flags = OMAP_I2C_FLAG_NO_FIFO |
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OMAP_I2C_FLAG_SIMPLE_CLOCK |
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OMAP_I2C_FLAG_16BIT_DATA_REG |
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OMAP_I2C_FLAG_BUS_SHIFT_2,
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};
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/* I2C1 */
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static struct omap_hwmod omap2420_i2c1_hwmod = {
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.name = "i2c1",
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.mpu_irqs = omap2_i2c1_mpu_irqs,
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.sdma_reqs = omap2_i2c1_sdma_reqs,
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.main_clk = "i2c1_fck",
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.prcm = {
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.omap2 = {
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.module_offs = CORE_MOD,
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.prcm_reg_id = 1,
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.module_bit = OMAP2420_EN_I2C1_SHIFT,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
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},
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},
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.class = &i2c_class,
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.dev_attr = &i2c_dev_attr,
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.flags = HWMOD_16BIT_REG,
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};
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/* I2C2 */
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static struct omap_hwmod omap2420_i2c2_hwmod = {
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.name = "i2c2",
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.mpu_irqs = omap2_i2c2_mpu_irqs,
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.sdma_reqs = omap2_i2c2_sdma_reqs,
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.main_clk = "i2c2_fck",
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.prcm = {
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.omap2 = {
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.module_offs = CORE_MOD,
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.prcm_reg_id = 1,
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.module_bit = OMAP2420_EN_I2C2_SHIFT,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
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},
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},
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.class = &i2c_class,
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.dev_attr = &i2c_dev_attr,
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.flags = HWMOD_16BIT_REG,
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};
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/* dma attributes */
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static struct omap_dma_dev_attr dma_dev_attr = {
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.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
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IS_CSSA_32 | IS_CDSA_32,
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.lch_count = 32,
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};
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static struct omap_hwmod omap2420_dma_system_hwmod = {
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.name = "dma",
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.class = &omap2xxx_dma_hwmod_class,
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.mpu_irqs = omap2_dma_system_irqs,
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.main_clk = "core_l3_ck",
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.dev_attr = &dma_dev_attr,
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.flags = HWMOD_NO_IDLEST,
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};
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/* mailbox */
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static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
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{ .name = "dsp", .irq = 26 },
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{ .name = "iva", .irq = 34 },
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{ .irq = -1 }
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};
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static struct omap_hwmod omap2420_mailbox_hwmod = {
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.name = "mailbox",
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.class = &omap2xxx_mailbox_hwmod_class,
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.mpu_irqs = omap2420_mailbox_irqs,
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.main_clk = "mailboxes_ick",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
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.module_offs = CORE_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
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},
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},
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};
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/*
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* 'mcbsp' class
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* multi channel buffered serial port controller
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*/
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static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
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.name = "mcbsp",
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};
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static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
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{ .role = "pad_fck", .clk = "mcbsp_clks" },
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{ .role = "prcm_fck", .clk = "func_96m_ck" },
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};
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/* mcbsp1 */
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static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
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{ .name = "tx", .irq = 59 },
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{ .name = "rx", .irq = 60 },
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{ .irq = -1 }
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};
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static struct omap_hwmod omap2420_mcbsp1_hwmod = {
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.name = "mcbsp1",
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.class = &omap2420_mcbsp_hwmod_class,
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.mpu_irqs = omap2420_mcbsp1_irqs,
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.sdma_reqs = omap2_mcbsp1_sdma_reqs,
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.main_clk = "mcbsp1_fck",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
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.module_offs = CORE_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
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},
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},
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.opt_clks = mcbsp_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
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};
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/* mcbsp2 */
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static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
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{ .name = "tx", .irq = 62 },
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{ .name = "rx", .irq = 63 },
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{ .irq = -1 }
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};
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static struct omap_hwmod omap2420_mcbsp2_hwmod = {
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.name = "mcbsp2",
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.class = &omap2420_mcbsp_hwmod_class,
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.mpu_irqs = omap2420_mcbsp2_irqs,
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.sdma_reqs = omap2_mcbsp2_sdma_reqs,
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.main_clk = "mcbsp2_fck",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
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.module_offs = CORE_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
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},
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},
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.opt_clks = mcbsp_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
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};
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static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
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.rev_offs = 0x3c,
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.sysc_offs = 0x64,
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.syss_offs = 0x68,
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.sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
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.name = "msdi",
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.sysc = &omap2420_msdi_sysc,
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.reset = &omap_msdi_reset,
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};
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/* msdi1 */
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static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
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{ .irq = 83 },
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{ .irq = -1 }
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};
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static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
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{ .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */
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{ .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */
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{ .dma_req = -1 }
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};
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static struct omap_hwmod omap2420_msdi1_hwmod = {
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.name = "msdi1",
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.class = &omap2420_msdi_hwmod_class,
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.mpu_irqs = omap2420_msdi1_irqs,
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.sdma_reqs = omap2420_msdi1_sdma_reqs,
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.main_clk = "mmc_fck",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP2420_EN_MMC_SHIFT,
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.module_offs = CORE_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
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},
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},
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.flags = HWMOD_16BIT_REG,
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};
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/* HDQ1W/1-wire */
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static struct omap_hwmod omap2420_hdq1w_hwmod = {
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.name = "hdq1w",
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.mpu_irqs = omap2_hdq1w_mpu_irqs,
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.main_clk = "hdq_fck",
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.prcm = {
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.omap2 = {
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.module_offs = CORE_MOD,
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.prcm_reg_id = 1,
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.module_bit = OMAP24XX_EN_HDQ_SHIFT,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
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},
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},
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.class = &omap2_hdq1w_class,
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};
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/*
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* interfaces
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*/
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/* L4 CORE -> I2C1 interface */
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static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2420_i2c1_hwmod,
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.clk = "i2c1_ick",
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.addr = omap2_i2c1_addr_space,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4 CORE -> I2C2 interface */
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static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2420_i2c2_hwmod,
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.clk = "i2c2_ick",
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.addr = omap2_i2c2_addr_space,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* IVA <- L3 interface */
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static struct omap_hwmod_ocp_if omap2420_l3__iva = {
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.master = &omap2xxx_l3_main_hwmod,
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.slave = &omap2420_iva_hwmod,
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.clk = "core_l3_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* DSP <- L3 interface */
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static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
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.master = &omap2xxx_l3_main_hwmod,
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.slave = &omap2420_dsp_hwmod,
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.clk = "dsp_ick",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
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{
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.pa_start = 0x48028000,
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.pa_end = 0x48028000 + SZ_1K - 1,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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/* l4_wkup -> timer1 */
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static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
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.master = &omap2xxx_l4_wkup_hwmod,
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.slave = &omap2xxx_timer1_hwmod,
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.clk = "gpt1_ick",
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.addr = omap2420_timer1_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_wkup -> wd_timer2 */
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static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
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{
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.pa_start = 0x48022000,
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.pa_end = 0x4802207f,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
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.master = &omap2xxx_l4_wkup_hwmod,
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.slave = &omap2xxx_wd_timer2_hwmod,
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.clk = "mpu_wdt_ick",
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.addr = omap2420_wd_timer2_addrs,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_wkup -> gpio1 */
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static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
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{
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.pa_start = 0x48018000,
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.pa_end = 0x480181ff,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
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.master = &omap2xxx_l4_wkup_hwmod,
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.slave = &omap2xxx_gpio1_hwmod,
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.clk = "gpios_ick",
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.addr = omap2420_gpio1_addr_space,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_wkup -> gpio2 */
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static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
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{
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.pa_start = 0x4801a000,
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.pa_end = 0x4801a1ff,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
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.master = &omap2xxx_l4_wkup_hwmod,
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.slave = &omap2xxx_gpio2_hwmod,
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.clk = "gpios_ick",
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.addr = omap2420_gpio2_addr_space,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_wkup -> gpio3 */
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static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
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{
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.pa_start = 0x4801c000,
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.pa_end = 0x4801c1ff,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
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.master = &omap2xxx_l4_wkup_hwmod,
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.slave = &omap2xxx_gpio3_hwmod,
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.clk = "gpios_ick",
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.addr = omap2420_gpio3_addr_space,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_wkup -> gpio4 */
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static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
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{
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.pa_start = 0x4801e000,
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.pa_end = 0x4801e1ff,
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.flags = ADDR_TYPE_RT
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},
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{ }
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};
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static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
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.master = &omap2xxx_l4_wkup_hwmod,
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.slave = &omap2xxx_gpio4_hwmod,
|
|
.clk = "gpios_ick",
|
|
.addr = omap2420_gpio4_addr_space,
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* dma_system -> L3 */
|
|
static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
|
|
.master = &omap2420_dma_system_hwmod,
|
|
.slave = &omap2xxx_l3_main_hwmod,
|
|
.clk = "core_l3_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_core -> dma_system */
|
|
static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
|
|
.master = &omap2xxx_l4_core_hwmod,
|
|
.slave = &omap2420_dma_system_hwmod,
|
|
.clk = "sdma_ick",
|
|
.addr = omap2_dma_system_addrs,
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_core -> mailbox */
|
|
static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
|
|
.master = &omap2xxx_l4_core_hwmod,
|
|
.slave = &omap2420_mailbox_hwmod,
|
|
.addr = omap2_mailbox_addrs,
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_core -> mcbsp1 */
|
|
static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
|
|
.master = &omap2xxx_l4_core_hwmod,
|
|
.slave = &omap2420_mcbsp1_hwmod,
|
|
.clk = "mcbsp1_ick",
|
|
.addr = omap2_mcbsp1_addrs,
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_core -> mcbsp2 */
|
|
static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
|
|
.master = &omap2xxx_l4_core_hwmod,
|
|
.slave = &omap2420_mcbsp2_hwmod,
|
|
.clk = "mcbsp2_ick",
|
|
.addr = omap2xxx_mcbsp2_addrs,
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = {
|
|
{
|
|
.pa_start = 0x4809c000,
|
|
.pa_end = 0x4809c000 + SZ_128 - 1,
|
|
.flags = ADDR_TYPE_RT,
|
|
},
|
|
{ }
|
|
};
|
|
|
|
/* l4_core -> msdi1 */
|
|
static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
|
|
.master = &omap2xxx_l4_core_hwmod,
|
|
.slave = &omap2420_msdi1_hwmod,
|
|
.clk = "mmc_ick",
|
|
.addr = omap2420_msdi1_addrs,
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_core -> hdq1w interface */
|
|
static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
|
|
.master = &omap2xxx_l4_core_hwmod,
|
|
.slave = &omap2420_hdq1w_hwmod,
|
|
.clk = "hdq_ick",
|
|
.addr = omap2_hdq1w_addr_space,
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
.flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
|
|
};
|
|
|
|
|
|
/* l4_wkup -> 32ksync_counter */
|
|
static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
|
|
{
|
|
.pa_start = 0x48004000,
|
|
.pa_end = 0x4800401f,
|
|
.flags = ADDR_TYPE_RT
|
|
},
|
|
{ }
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
|
|
.master = &omap2xxx_l4_wkup_hwmod,
|
|
.slave = &omap2xxx_counter_32k_hwmod,
|
|
.clk = "sync_32k_ick",
|
|
.addr = omap2420_counter_32k_addrs,
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
|
|
&omap2xxx_l3_main__l4_core,
|
|
&omap2xxx_mpu__l3_main,
|
|
&omap2xxx_dss__l3,
|
|
&omap2xxx_l4_core__mcspi1,
|
|
&omap2xxx_l4_core__mcspi2,
|
|
&omap2xxx_l4_core__l4_wkup,
|
|
&omap2_l4_core__uart1,
|
|
&omap2_l4_core__uart2,
|
|
&omap2_l4_core__uart3,
|
|
&omap2420_l4_core__i2c1,
|
|
&omap2420_l4_core__i2c2,
|
|
&omap2420_l3__iva,
|
|
&omap2420_l3__dsp,
|
|
&omap2420_l4_wkup__timer1,
|
|
&omap2xxx_l4_core__timer2,
|
|
&omap2xxx_l4_core__timer3,
|
|
&omap2xxx_l4_core__timer4,
|
|
&omap2xxx_l4_core__timer5,
|
|
&omap2xxx_l4_core__timer6,
|
|
&omap2xxx_l4_core__timer7,
|
|
&omap2xxx_l4_core__timer8,
|
|
&omap2xxx_l4_core__timer9,
|
|
&omap2xxx_l4_core__timer10,
|
|
&omap2xxx_l4_core__timer11,
|
|
&omap2xxx_l4_core__timer12,
|
|
&omap2420_l4_wkup__wd_timer2,
|
|
&omap2xxx_l4_core__dss,
|
|
&omap2xxx_l4_core__dss_dispc,
|
|
&omap2xxx_l4_core__dss_rfbi,
|
|
&omap2xxx_l4_core__dss_venc,
|
|
&omap2420_l4_wkup__gpio1,
|
|
&omap2420_l4_wkup__gpio2,
|
|
&omap2420_l4_wkup__gpio3,
|
|
&omap2420_l4_wkup__gpio4,
|
|
&omap2420_dma_system__l3,
|
|
&omap2420_l4_core__dma_system,
|
|
&omap2420_l4_core__mailbox,
|
|
&omap2420_l4_core__mcbsp1,
|
|
&omap2420_l4_core__mcbsp2,
|
|
&omap2420_l4_core__msdi1,
|
|
&omap2420_l4_core__hdq1w,
|
|
&omap2420_l4_wkup__counter_32k,
|
|
NULL,
|
|
};
|
|
|
|
int __init omap2420_hwmod_init(void)
|
|
{
|
|
omap_hwmod_init();
|
|
return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
|
|
}
|