forked from Minki/linux
b1012ca8dc
The VT-d spec requires (10.4.4 Global Command Register, TE field) that: Hardware implementations supporting DMA draining must drain any in-flight DMA read/write requests queued within the Root-Complex before completing the translation enable command and reflecting the status of the command through the TES field in the Global Status register. Unfortunately, some integrated graphic devices fail to do so after some kind of power state transition. As the result, the system might stuck in iommu_disable_translation(), waiting for the completion of TE transition. This provides a quirk list for those devices and skips TE disabling if the qurik hits. Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=208363 Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=206571 Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Tested-by: Koba Ko <koba.ko@canonical.com> Tested-by: Jun Miao <jun.miao@windriver.com> Cc: Ashok Raj <ashok.raj@intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20200723013437.2268-1-baolu.lu@linux.intel.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
287 lines
7.6 KiB
C
287 lines
7.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2006, Intel Corporation.
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*
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* Copyright (C) Ashok Raj <ashok.raj@intel.com>
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* Copyright (C) Shaohua Li <shaohua.li@intel.com>
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*/
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#ifndef __DMAR_H__
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#define __DMAR_H__
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#include <linux/acpi.h>
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#include <linux/types.h>
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#include <linux/msi.h>
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#include <linux/irqreturn.h>
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#include <linux/rwsem.h>
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#include <linux/rculist.h>
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struct acpi_dmar_header;
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#ifdef CONFIG_X86
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# define DMAR_UNITS_SUPPORTED MAX_IO_APICS
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#else
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# define DMAR_UNITS_SUPPORTED 64
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#endif
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/* DMAR Flags */
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#define DMAR_INTR_REMAP 0x1
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#define DMAR_X2APIC_OPT_OUT 0x2
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#define DMAR_PLATFORM_OPT_IN 0x4
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struct intel_iommu;
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struct dmar_dev_scope {
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struct device __rcu *dev;
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u8 bus;
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u8 devfn;
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};
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#ifdef CONFIG_DMAR_TABLE
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extern struct acpi_table_header *dmar_tbl;
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struct dmar_drhd_unit {
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struct list_head list; /* list of drhd units */
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struct acpi_dmar_header *hdr; /* ACPI header */
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u64 reg_base_addr; /* register base address*/
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struct dmar_dev_scope *devices;/* target device array */
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int devices_cnt; /* target device count */
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u16 segment; /* PCI domain */
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u8 ignored:1; /* ignore drhd */
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u8 include_all:1;
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u8 gfx_dedicated:1; /* graphic dedicated */
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struct intel_iommu *iommu;
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};
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struct dmar_pci_path {
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u8 bus;
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u8 device;
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u8 function;
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};
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struct dmar_pci_notify_info {
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struct pci_dev *dev;
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unsigned long event;
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int bus;
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u16 seg;
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u16 level;
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struct dmar_pci_path path[];
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} __attribute__((packed));
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extern struct rw_semaphore dmar_global_lock;
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extern struct list_head dmar_drhd_units;
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#define for_each_drhd_unit(drhd) \
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list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \
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dmar_rcu_check())
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#define for_each_active_drhd_unit(drhd) \
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list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \
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dmar_rcu_check()) \
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if (drhd->ignored) {} else
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#define for_each_active_iommu(i, drhd) \
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list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \
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dmar_rcu_check()) \
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if (i=drhd->iommu, drhd->ignored) {} else
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#define for_each_iommu(i, drhd) \
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list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \
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dmar_rcu_check()) \
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if (i=drhd->iommu, 0) {} else
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static inline bool dmar_rcu_check(void)
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{
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return rwsem_is_locked(&dmar_global_lock) ||
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system_state == SYSTEM_BOOTING;
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}
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#define dmar_rcu_dereference(p) rcu_dereference_check((p), dmar_rcu_check())
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#define for_each_dev_scope(devs, cnt, i, tmp) \
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for ((i) = 0; ((tmp) = (i) < (cnt) ? \
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dmar_rcu_dereference((devs)[(i)].dev) : NULL, (i) < (cnt)); \
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(i)++)
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#define for_each_active_dev_scope(devs, cnt, i, tmp) \
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for_each_dev_scope((devs), (cnt), (i), (tmp)) \
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if (!(tmp)) { continue; } else
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extern int dmar_table_init(void);
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extern int dmar_dev_scope_init(void);
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extern void dmar_register_bus_notifier(void);
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extern int dmar_parse_dev_scope(void *start, void *end, int *cnt,
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struct dmar_dev_scope **devices, u16 segment);
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extern void *dmar_alloc_dev_scope(void *start, void *end, int *cnt);
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extern void dmar_free_dev_scope(struct dmar_dev_scope **devices, int *cnt);
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extern int dmar_insert_dev_scope(struct dmar_pci_notify_info *info,
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void *start, void*end, u16 segment,
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struct dmar_dev_scope *devices,
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int devices_cnt);
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extern int dmar_remove_dev_scope(struct dmar_pci_notify_info *info,
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u16 segment, struct dmar_dev_scope *devices,
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int count);
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/* Intel IOMMU detection */
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extern int detect_intel_iommu(void);
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extern int enable_drhd_fault_handling(void);
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extern int dmar_device_add(acpi_handle handle);
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extern int dmar_device_remove(acpi_handle handle);
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static inline int dmar_res_noop(struct acpi_dmar_header *hdr, void *arg)
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{
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return 0;
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}
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#ifdef CONFIG_INTEL_IOMMU
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extern int iommu_detected, no_iommu;
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extern int intel_iommu_init(void);
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extern void intel_iommu_shutdown(void);
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extern int dmar_parse_one_rmrr(struct acpi_dmar_header *header, void *arg);
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extern int dmar_parse_one_atsr(struct acpi_dmar_header *header, void *arg);
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extern int dmar_check_one_atsr(struct acpi_dmar_header *hdr, void *arg);
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extern int dmar_release_one_atsr(struct acpi_dmar_header *hdr, void *arg);
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extern int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert);
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extern int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info);
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#else /* !CONFIG_INTEL_IOMMU: */
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static inline int intel_iommu_init(void) { return -ENODEV; }
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static inline void intel_iommu_shutdown(void) { }
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#define dmar_parse_one_rmrr dmar_res_noop
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#define dmar_parse_one_atsr dmar_res_noop
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#define dmar_check_one_atsr dmar_res_noop
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#define dmar_release_one_atsr dmar_res_noop
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static inline int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info)
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{
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return 0;
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}
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static inline int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
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{
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return 0;
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}
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#endif /* CONFIG_INTEL_IOMMU */
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#ifdef CONFIG_IRQ_REMAP
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extern int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert);
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#else /* CONFIG_IRQ_REMAP */
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static inline int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
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{ return 0; }
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#endif /* CONFIG_IRQ_REMAP */
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extern bool dmar_platform_optin(void);
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#else /* CONFIG_DMAR_TABLE */
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static inline int dmar_device_add(void *handle)
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{
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return 0;
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}
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static inline int dmar_device_remove(void *handle)
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{
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return 0;
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}
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static inline bool dmar_platform_optin(void)
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{
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return false;
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}
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#endif /* CONFIG_DMAR_TABLE */
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struct irte {
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union {
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/* Shared between remapped and posted mode*/
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struct {
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__u64 present : 1, /* 0 */
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fpd : 1, /* 1 */
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__res0 : 6, /* 2 - 6 */
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avail : 4, /* 8 - 11 */
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__res1 : 3, /* 12 - 14 */
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pst : 1, /* 15 */
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vector : 8, /* 16 - 23 */
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__res2 : 40; /* 24 - 63 */
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};
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/* Remapped mode */
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struct {
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__u64 r_present : 1, /* 0 */
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r_fpd : 1, /* 1 */
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dst_mode : 1, /* 2 */
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redir_hint : 1, /* 3 */
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trigger_mode : 1, /* 4 */
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dlvry_mode : 3, /* 5 - 7 */
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r_avail : 4, /* 8 - 11 */
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r_res0 : 4, /* 12 - 15 */
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r_vector : 8, /* 16 - 23 */
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r_res1 : 8, /* 24 - 31 */
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dest_id : 32; /* 32 - 63 */
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};
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/* Posted mode */
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struct {
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__u64 p_present : 1, /* 0 */
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p_fpd : 1, /* 1 */
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p_res0 : 6, /* 2 - 7 */
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p_avail : 4, /* 8 - 11 */
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p_res1 : 2, /* 12 - 13 */
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p_urgent : 1, /* 14 */
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p_pst : 1, /* 15 */
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p_vector : 8, /* 16 - 23 */
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p_res2 : 14, /* 24 - 37 */
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pda_l : 26; /* 38 - 63 */
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};
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__u64 low;
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};
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union {
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/* Shared between remapped and posted mode*/
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struct {
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__u64 sid : 16, /* 64 - 79 */
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sq : 2, /* 80 - 81 */
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svt : 2, /* 82 - 83 */
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__res3 : 44; /* 84 - 127 */
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};
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/* Posted mode*/
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struct {
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__u64 p_sid : 16, /* 64 - 79 */
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p_sq : 2, /* 80 - 81 */
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p_svt : 2, /* 82 - 83 */
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p_res3 : 12, /* 84 - 95 */
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pda_h : 32; /* 96 - 127 */
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};
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__u64 high;
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};
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};
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static inline void dmar_copy_shared_irte(struct irte *dst, struct irte *src)
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{
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dst->present = src->present;
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dst->fpd = src->fpd;
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dst->avail = src->avail;
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dst->pst = src->pst;
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dst->vector = src->vector;
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dst->sid = src->sid;
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dst->sq = src->sq;
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dst->svt = src->svt;
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}
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#define PDA_LOW_BIT 26
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#define PDA_HIGH_BIT 32
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/* Can't use the common MSI interrupt functions
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* since DMAR is not a pci device
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*/
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struct irq_data;
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extern void dmar_msi_unmask(struct irq_data *data);
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extern void dmar_msi_mask(struct irq_data *data);
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extern void dmar_msi_read(int irq, struct msi_msg *msg);
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extern void dmar_msi_write(int irq, struct msi_msg *msg);
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extern int dmar_set_interrupt(struct intel_iommu *iommu);
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extern irqreturn_t dmar_fault(int irq, void *dev_id);
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extern int dmar_alloc_hwirq(int id, int node, void *arg);
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extern void dmar_free_hwirq(int irq);
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#endif /* __DMAR_H__ */
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