b7187e001a
This patch adds support for RZ/G1C (r8a77470) SoC. RZ/G1C SoC has a PLL register shared between hsusb0 and hsusb1. Compared to other RZ/G1 and R-Car Gen2/3, USB Host needs to deassert the pll reset. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-and-Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> |
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Kconfig | ||
Makefile | ||
phy-rcar-gen2.c | ||
phy-rcar-gen3-pcie.c | ||
phy-rcar-gen3-usb2.c | ||
phy-rcar-gen3-usb3.c |