4f4eebf26f
For retrieving info like interface MAC addresses, packet parser key extraction config etc currently a command is sent to firmware and firmware which periodically polls for commands, processes these and returns the info. This is resulting in interface initialization taking lot of time. To optimize this a memory region is shared between firmware and this driver, firmware while booting puts static info like these into that region for driver to read directly without using commands. With this - Logic for retrieving packet parser extraction config via commands is removed and repalced with using the shared 'fwdata' structure. - Now RVU MSIX vector address is also retrieved from this fwdata struct instead of from CSR. Otherwise when kexec/kdump crash kernel loads CSR will have a IOVA setup by primary kernel which impacts RVU PF/VF's interrupts. - Also added a mbox handler for PF/VF interfaces to retrieve their MAC addresses from AF. Signed-off-by: Linu Cherian <lcherian@marvell.com> Signed-off-by: Christina Jacob <cjacob@marvell.com> Signed-off-by: Rakesh Babu <rsaladi2@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
143 lines
4.4 KiB
C
143 lines
4.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Marvell OcteonTx2 CGX driver
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*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef CGX_H
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#define CGX_H
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#include "mbox.h"
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#include "cgx_fw_if.h"
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/* PCI device IDs */
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#define PCI_DEVID_OCTEONTX2_CGX 0xA059
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/* PCI BAR nos */
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#define PCI_CFG_REG_BAR_NUM 0
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#define CGX_ID_MASK 0x7
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#define MAX_LMAC_PER_CGX 4
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#define CGX_FIFO_LEN 65536 /* 64K for both Rx & Tx */
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#define CGX_OFFSET(x) ((x) * MAX_LMAC_PER_CGX)
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/* Registers */
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#define CGXX_CMRX_CFG 0x00
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#define CMR_EN BIT_ULL(55)
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#define DATA_PKT_TX_EN BIT_ULL(53)
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#define DATA_PKT_RX_EN BIT_ULL(54)
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#define CGX_LMAC_TYPE_SHIFT 40
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#define CGX_LMAC_TYPE_MASK 0xF
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#define CGXX_CMRX_INT 0x040
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#define FW_CGX_INT BIT_ULL(1)
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#define CGXX_CMRX_INT_ENA_W1S 0x058
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#define CGXX_CMRX_RX_ID_MAP 0x060
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#define CGXX_CMRX_RX_STAT0 0x070
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#define CGXX_CMRX_RX_LMACS 0x128
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#define CGXX_CMRX_RX_DMAC_CTL0 0x1F8
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#define CGX_DMAC_CTL0_CAM_ENABLE BIT_ULL(3)
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#define CGX_DMAC_CAM_ACCEPT BIT_ULL(3)
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#define CGX_DMAC_MCAST_MODE BIT_ULL(1)
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#define CGX_DMAC_BCAST_MODE BIT_ULL(0)
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#define CGXX_CMRX_RX_DMAC_CAM0 0x200
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#define CGX_DMAC_CAM_ADDR_ENABLE BIT_ULL(48)
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#define CGXX_CMRX_RX_DMAC_CAM1 0x400
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#define CGX_RX_DMAC_ADR_MASK GENMASK_ULL(47, 0)
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#define CGXX_CMRX_TX_STAT0 0x700
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#define CGXX_SCRATCH0_REG 0x1050
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#define CGXX_SCRATCH1_REG 0x1058
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#define CGX_CONST 0x2000
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#define CGXX_SPUX_CONTROL1 0x10000
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#define CGXX_SPUX_CONTROL1_LBK BIT_ULL(14)
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#define CGXX_GMP_PCS_MRX_CTL 0x30000
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#define CGXX_GMP_PCS_MRX_CTL_LBK BIT_ULL(14)
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#define CGXX_SMUX_RX_FRM_CTL 0x20020
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#define CGX_SMUX_RX_FRM_CTL_CTL_BCK BIT_ULL(3)
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#define CGXX_GMP_GMI_RXX_FRM_CTL 0x38028
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#define CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK BIT_ULL(3)
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#define CGXX_SMUX_TX_CTL 0x20178
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#define CGXX_SMUX_TX_PAUSE_PKT_TIME 0x20110
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#define CGXX_SMUX_TX_PAUSE_PKT_INTERVAL 0x20120
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#define CGXX_GMP_GMI_TX_PAUSE_PKT_TIME 0x38230
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#define CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL 0x38248
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#define CGX_SMUX_TX_CTL_L2P_BP_CONV BIT_ULL(7)
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#define CGXX_CMR_RX_OVR_BP 0x130
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#define CGX_CMR_RX_OVR_BP_EN(X) BIT_ULL(((X) + 8))
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#define CGX_CMR_RX_OVR_BP_BP(X) BIT_ULL(((X) + 4))
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#define CGX_COMMAND_REG CGXX_SCRATCH1_REG
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#define CGX_EVENT_REG CGXX_SCRATCH0_REG
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#define CGX_CMD_TIMEOUT 2200 /* msecs */
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#define DEFAULT_PAUSE_TIME 0x7FF
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#define CGX_NVEC 37
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#define CGX_LMAC_FWI 0
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enum cgx_nix_stat_type {
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NIX_STATS_RX,
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NIX_STATS_TX,
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};
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enum LMAC_TYPE {
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LMAC_MODE_SGMII = 0,
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LMAC_MODE_XAUI = 1,
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LMAC_MODE_RXAUI = 2,
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LMAC_MODE_10G_R = 3,
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LMAC_MODE_40G_R = 4,
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LMAC_MODE_QSGMII = 6,
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LMAC_MODE_25G_R = 7,
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LMAC_MODE_50G_R = 8,
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LMAC_MODE_100G_R = 9,
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LMAC_MODE_USXGMII = 10,
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LMAC_MODE_MAX,
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};
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struct cgx_link_event {
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struct cgx_link_user_info link_uinfo;
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u8 cgx_id;
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u8 lmac_id;
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};
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/**
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* struct cgx_event_cb
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* @notify_link_chg: callback for link change notification
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* @data: data passed to callback function
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*/
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struct cgx_event_cb {
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int (*notify_link_chg)(struct cgx_link_event *event, void *data);
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void *data;
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};
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extern struct pci_driver cgx_driver;
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int cgx_get_cgxcnt_max(void);
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int cgx_get_cgxid(void *cgxd);
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int cgx_get_lmac_cnt(void *cgxd);
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void *cgx_get_pdata(int cgx_id);
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int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind);
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int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id);
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int cgx_lmac_evh_unregister(void *cgxd, int lmac_id);
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int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat);
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int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat);
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int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable);
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int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable);
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int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr);
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u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id);
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void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable);
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void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable);
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int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable);
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int cgx_get_link_info(void *cgxd, int lmac_id,
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struct cgx_link_user_info *linfo);
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int cgx_lmac_linkup_start(void *cgxd);
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int cgx_get_fwdata_base(u64 *base);
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int cgx_lmac_get_pause_frm(void *cgxd, int lmac_id,
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u8 *tx_pause, u8 *rx_pause);
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int cgx_lmac_set_pause_frm(void *cgxd, int lmac_id,
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u8 tx_pause, u8 rx_pause);
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#endif /* CGX_H */
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