forked from Minki/linux
291b38a756
-----BEGIN PGP SIGNATURE----- iQIVAwUAWPiW6vSw1s6N8H32AQLOrw/+NTqGf7bjq+64YKS6NfR0XDgE+wNJltGO ck7zJW3NHIg76RNu8s0I9xg5aVmwizz3Z5DGROZquaolnezux4tQihZ3AFyxIzLc +Y3WHYagcML7yFfjl/WznCLRD5EW3yPln4lCvQO0nW/xICRYeRI057JaIbi2Dtek BhcXt3c4AjXDLdYJkgtHV3p2R2mt8hcdFdWqqx6s7JaIThZNRGNzxAgtbcB9k5IW HVG9ZEIL73VBYWHrYivzjHYF5rBnNCPt87eOwDQeTOSkhv8te+u9k+bH8vxZw1T0 XUtDrLBndKiuVo2GUfLkkF8LItx3Q9eLCJYy0joaIliyPqTEsPx9KjQ+Af0cxS9s ZPCZ5SYf96stKmDeL5xaMfrAmeyVHJ4lc4JTOqdzbIT8blsOSfYO/03p0ALShSDv /RQLaKGlf8Bjoy8PwKFcXb4sIDufcd/U1Av/EMFXxOfgN/u2JUkGKq6EaIM5B68L fHPje+aR9VNELPmPjwNOWtmN4I79EH3EItQf7zv0KG+UeKhcHLx/EAcSJ3ZRKEkH Lathg7pPOEJGArPiVO79TZzBG01ADn1aiwv65XObMzNZ+54xI/mN/Y1DNF/kL5jU XzvNzEjFt8mwMIZGVNdAt4+pDyMfIZGZSyUkSRKFnaQZMIvQrfQIU9RLBYLX5eOx +/p0VkIwDpg= =lbS7 -----END PGP SIGNATURE----- Merge tag 'hwparam-20170420' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs Pull hw lockdown support from David Howells: "Annotation of module parameters that configure hardware resources including ioports, iomem addresses, irq lines and dma channels. This allows a future patch to prohibit the use of such module parameters to prevent that hardware from being abused to gain access to the running kernel image as part of locking the kernel down under UEFI secure boot conditions. Annotations are made by changing: module_param(n, t, p) module_param_named(n, v, t, p) module_param_array(n, t, m, p) to: module_param_hw(n, t, hwtype, p) module_param_hw_named(n, v, t, hwtype, p) module_param_hw_array(n, t, hwtype, m, p) where the module parameter refers to a hardware setting hwtype specifies the type of the resource being configured. This can be one of: ioport Module parameter configures an I/O port iomem Module parameter configures an I/O mem address ioport_or_iomem Module parameter could be either (runtime set) irq Module parameter configures an I/O port dma Module parameter configures a DMA channel dma_addr Module parameter configures a DMA buffer address other Module parameter configures some other value Note that the hwtype is compile checked, but not currently stored (the lockdown code probably won't require it). It is, however, there for future use. A bonus is that the hwtype can also be used for grepping. The intention is for the kernel to ignore or reject attempts to set annotated module parameters if lockdown is enabled. This applies to options passed on the boot command line, passed to insmod/modprobe or direct twiddling in /sys/module/ parameter files. The module initialisation then needs to handle the parameter not being set, by (1) giving an error, (2) probing for a value or (3) using a reasonable default. What I can't do is just reject a module out of hand because it may take a hardware setting in the module parameters. Some important modules, some ipmi stuff for instance, both probe for hardware and allow hardware to be manually specified; if the driver is aborts with any error, you don't get any ipmi hardware. Further, trying to do this entirely in the module initialisation code doesn't protect against sysfs twiddling. [!] Note that in and of itself, this series of patches should have no effect on the the size of the kernel or code execution - that is left to a patch in the next series to effect. It does mark annotated kernel parameters with a KERNEL_PARAM_FL_HWPARAM flag in an already existing field" * tag 'hwparam-20170420' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs: (38 commits) Annotate hardware config module parameters in sound/pci/ Annotate hardware config module parameters in sound/oss/ Annotate hardware config module parameters in sound/isa/ Annotate hardware config module parameters in sound/drivers/ Annotate hardware config module parameters in fs/pstore/ Annotate hardware config module parameters in drivers/watchdog/ Annotate hardware config module parameters in drivers/video/ Annotate hardware config module parameters in drivers/tty/ Annotate hardware config module parameters in drivers/staging/vme/ Annotate hardware config module parameters in drivers/staging/speakup/ Annotate hardware config module parameters in drivers/staging/media/ Annotate hardware config module parameters in drivers/scsi/ Annotate hardware config module parameters in drivers/pcmcia/ Annotate hardware config module parameters in drivers/pci/hotplug/ Annotate hardware config module parameters in drivers/parport/ Annotate hardware config module parameters in drivers/net/wireless/ Annotate hardware config module parameters in drivers/net/wan/ Annotate hardware config module parameters in drivers/net/irda/ Annotate hardware config module parameters in drivers/net/hamradio/ Annotate hardware config module parameters in drivers/net/ethernet/ ...
442 lines
13 KiB
C
442 lines
13 KiB
C
/*
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* GPIO driver for the ACCES 104-DIO-48E series
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* Copyright (C) 2016 William Breathitt Gray
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* This driver supports the following ACCES devices: 104-DIO-48E and
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* 104-DIO-24E.
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*/
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/irqdesc.h>
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#include <linux/isa.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/spinlock.h>
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#define DIO48E_EXTENT 16
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#define MAX_NUM_DIO48E max_num_isa_dev(DIO48E_EXTENT)
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static unsigned int base[MAX_NUM_DIO48E];
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static unsigned int num_dio48e;
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module_param_hw_array(base, uint, ioport, &num_dio48e, 0);
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MODULE_PARM_DESC(base, "ACCES 104-DIO-48E base addresses");
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static unsigned int irq[MAX_NUM_DIO48E];
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module_param_hw_array(irq, uint, irq, NULL, 0);
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MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line numbers");
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/**
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* struct dio48e_gpio - GPIO device private data structure
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* @chip: instance of the gpio_chip
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* @io_state: bit I/O state (whether bit is set to input or output)
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* @out_state: output bits state
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* @control: Control registers state
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* @lock: synchronization lock to prevent I/O race conditions
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* @base: base port address of the GPIO device
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* @irq_mask: I/O bits affected by interrupts
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*/
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struct dio48e_gpio {
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struct gpio_chip chip;
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unsigned char io_state[6];
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unsigned char out_state[6];
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unsigned char control[2];
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raw_spinlock_t lock;
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unsigned base;
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unsigned char irq_mask;
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};
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static int dio48e_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned port = offset / 8;
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const unsigned mask = BIT(offset % 8);
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return !!(dio48egpio->io_state[port] & mask);
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}
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static int dio48e_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned io_port = offset / 8;
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const unsigned int control_port = io_port / 3;
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const unsigned control_addr = dio48egpio->base + 3 + control_port*4;
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unsigned long flags;
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unsigned control;
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raw_spin_lock_irqsave(&dio48egpio->lock, flags);
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/* Check if configuring Port C */
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if (io_port == 2 || io_port == 5) {
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/* Port C can be configured by nibble */
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if (offset % 8 > 3) {
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dio48egpio->io_state[io_port] |= 0xF0;
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dio48egpio->control[control_port] |= BIT(3);
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} else {
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dio48egpio->io_state[io_port] |= 0x0F;
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dio48egpio->control[control_port] |= BIT(0);
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}
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} else {
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dio48egpio->io_state[io_port] |= 0xFF;
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if (io_port == 0 || io_port == 3)
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dio48egpio->control[control_port] |= BIT(4);
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else
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dio48egpio->control[control_port] |= BIT(1);
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}
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control = BIT(7) | dio48egpio->control[control_port];
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outb(control, control_addr);
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control &= ~BIT(7);
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outb(control, control_addr);
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raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
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return 0;
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}
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static int dio48e_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
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int value)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned io_port = offset / 8;
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const unsigned int control_port = io_port / 3;
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const unsigned mask = BIT(offset % 8);
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const unsigned control_addr = dio48egpio->base + 3 + control_port*4;
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const unsigned out_port = (io_port > 2) ? io_port + 1 : io_port;
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unsigned long flags;
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unsigned control;
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raw_spin_lock_irqsave(&dio48egpio->lock, flags);
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/* Check if configuring Port C */
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if (io_port == 2 || io_port == 5) {
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/* Port C can be configured by nibble */
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if (offset % 8 > 3) {
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dio48egpio->io_state[io_port] &= 0x0F;
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dio48egpio->control[control_port] &= ~BIT(3);
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} else {
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dio48egpio->io_state[io_port] &= 0xF0;
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dio48egpio->control[control_port] &= ~BIT(0);
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}
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} else {
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dio48egpio->io_state[io_port] &= 0x00;
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if (io_port == 0 || io_port == 3)
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dio48egpio->control[control_port] &= ~BIT(4);
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else
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dio48egpio->control[control_port] &= ~BIT(1);
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}
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if (value)
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dio48egpio->out_state[io_port] |= mask;
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else
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dio48egpio->out_state[io_port] &= ~mask;
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control = BIT(7) | dio48egpio->control[control_port];
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outb(control, control_addr);
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outb(dio48egpio->out_state[io_port], dio48egpio->base + out_port);
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control &= ~BIT(7);
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outb(control, control_addr);
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raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
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return 0;
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}
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static int dio48e_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned port = offset / 8;
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const unsigned mask = BIT(offset % 8);
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const unsigned in_port = (port > 2) ? port + 1 : port;
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unsigned long flags;
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unsigned port_state;
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raw_spin_lock_irqsave(&dio48egpio->lock, flags);
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/* ensure that GPIO is set for input */
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if (!(dio48egpio->io_state[port] & mask)) {
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raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
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return -EINVAL;
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}
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port_state = inb(dio48egpio->base + in_port);
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raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
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return !!(port_state & mask);
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}
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static void dio48e_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned port = offset / 8;
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const unsigned mask = BIT(offset % 8);
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const unsigned out_port = (port > 2) ? port + 1 : port;
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unsigned long flags;
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raw_spin_lock_irqsave(&dio48egpio->lock, flags);
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if (value)
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dio48egpio->out_state[port] |= mask;
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else
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dio48egpio->out_state[port] &= ~mask;
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outb(dio48egpio->out_state[port], dio48egpio->base + out_port);
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raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
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}
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static void dio48e_gpio_set_multiple(struct gpio_chip *chip,
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unsigned long *mask, unsigned long *bits)
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{
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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unsigned int i;
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const unsigned int gpio_reg_size = 8;
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unsigned int port;
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unsigned int out_port;
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unsigned int bitmask;
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unsigned long flags;
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/* set bits are evaluated a gpio register size at a time */
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for (i = 0; i < chip->ngpio; i += gpio_reg_size) {
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/* no more set bits in this mask word; skip to the next word */
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if (!mask[BIT_WORD(i)]) {
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i = (BIT_WORD(i) + 1) * BITS_PER_LONG - gpio_reg_size;
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continue;
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}
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port = i / gpio_reg_size;
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out_port = (port > 2) ? port + 1 : port;
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bitmask = mask[BIT_WORD(i)] & bits[BIT_WORD(i)];
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raw_spin_lock_irqsave(&dio48egpio->lock, flags);
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/* update output state data and set device gpio register */
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dio48egpio->out_state[port] &= ~mask[BIT_WORD(i)];
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dio48egpio->out_state[port] |= bitmask;
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outb(dio48egpio->out_state[port], dio48egpio->base + out_port);
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raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
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/* prepare for next gpio register set */
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mask[BIT_WORD(i)] >>= gpio_reg_size;
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bits[BIT_WORD(i)] >>= gpio_reg_size;
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}
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}
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static void dio48e_irq_ack(struct irq_data *data)
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{
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}
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static void dio48e_irq_mask(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned long offset = irqd_to_hwirq(data);
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unsigned long flags;
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/* only bit 3 on each respective Port C supports interrupts */
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if (offset != 19 && offset != 43)
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return;
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raw_spin_lock_irqsave(&dio48egpio->lock, flags);
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if (offset == 19)
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dio48egpio->irq_mask &= ~BIT(0);
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else
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dio48egpio->irq_mask &= ~BIT(1);
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if (!dio48egpio->irq_mask)
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/* disable interrupts */
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inb(dio48egpio->base + 0xB);
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raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
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}
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static void dio48e_irq_unmask(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
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const unsigned long offset = irqd_to_hwirq(data);
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unsigned long flags;
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/* only bit 3 on each respective Port C supports interrupts */
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if (offset != 19 && offset != 43)
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return;
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raw_spin_lock_irqsave(&dio48egpio->lock, flags);
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if (!dio48egpio->irq_mask) {
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/* enable interrupts */
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outb(0x00, dio48egpio->base + 0xF);
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outb(0x00, dio48egpio->base + 0xB);
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}
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if (offset == 19)
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dio48egpio->irq_mask |= BIT(0);
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else
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dio48egpio->irq_mask |= BIT(1);
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raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
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}
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static int dio48e_irq_set_type(struct irq_data *data, unsigned flow_type)
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{
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const unsigned long offset = irqd_to_hwirq(data);
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/* only bit 3 on each respective Port C supports interrupts */
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if (offset != 19 && offset != 43)
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return -EINVAL;
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if (flow_type != IRQ_TYPE_NONE && flow_type != IRQ_TYPE_EDGE_RISING)
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return -EINVAL;
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return 0;
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}
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static struct irq_chip dio48e_irqchip = {
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.name = "104-dio-48e",
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.irq_ack = dio48e_irq_ack,
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.irq_mask = dio48e_irq_mask,
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.irq_unmask = dio48e_irq_unmask,
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.irq_set_type = dio48e_irq_set_type
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};
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static irqreturn_t dio48e_irq_handler(int irq, void *dev_id)
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{
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struct dio48e_gpio *const dio48egpio = dev_id;
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struct gpio_chip *const chip = &dio48egpio->chip;
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const unsigned long irq_mask = dio48egpio->irq_mask;
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unsigned long gpio;
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for_each_set_bit(gpio, &irq_mask, 2)
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generic_handle_irq(irq_find_mapping(chip->irqdomain,
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19 + gpio*24));
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raw_spin_lock(&dio48egpio->lock);
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outb(0x00, dio48egpio->base + 0xF);
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raw_spin_unlock(&dio48egpio->lock);
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return IRQ_HANDLED;
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}
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#define DIO48E_NGPIO 48
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static const char *dio48e_names[DIO48E_NGPIO] = {
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"PPI Group 0 Port A 0", "PPI Group 0 Port A 1", "PPI Group 0 Port A 2",
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"PPI Group 0 Port A 3", "PPI Group 0 Port A 4", "PPI Group 0 Port A 5",
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"PPI Group 0 Port A 6", "PPI Group 0 Port A 7", "PPI Group 0 Port B 0",
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"PPI Group 0 Port B 1", "PPI Group 0 Port B 2", "PPI Group 0 Port B 3",
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"PPI Group 0 Port B 4", "PPI Group 0 Port B 5", "PPI Group 0 Port B 6",
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"PPI Group 0 Port B 7", "PPI Group 0 Port C 0", "PPI Group 0 Port C 1",
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"PPI Group 0 Port C 2", "PPI Group 0 Port C 3", "PPI Group 0 Port C 4",
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"PPI Group 0 Port C 5", "PPI Group 0 Port C 6", "PPI Group 0 Port C 7",
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"PPI Group 1 Port A 0", "PPI Group 1 Port A 1", "PPI Group 1 Port A 2",
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"PPI Group 1 Port A 3", "PPI Group 1 Port A 4", "PPI Group 1 Port A 5",
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"PPI Group 1 Port A 6", "PPI Group 1 Port A 7", "PPI Group 1 Port B 0",
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"PPI Group 1 Port B 1", "PPI Group 1 Port B 2", "PPI Group 1 Port B 3",
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"PPI Group 1 Port B 4", "PPI Group 1 Port B 5", "PPI Group 1 Port B 6",
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"PPI Group 1 Port B 7", "PPI Group 1 Port C 0", "PPI Group 1 Port C 1",
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"PPI Group 1 Port C 2", "PPI Group 1 Port C 3", "PPI Group 1 Port C 4",
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"PPI Group 1 Port C 5", "PPI Group 1 Port C 6", "PPI Group 1 Port C 7"
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};
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static int dio48e_probe(struct device *dev, unsigned int id)
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{
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struct dio48e_gpio *dio48egpio;
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const char *const name = dev_name(dev);
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int err;
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dio48egpio = devm_kzalloc(dev, sizeof(*dio48egpio), GFP_KERNEL);
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if (!dio48egpio)
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return -ENOMEM;
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|
|
|
if (!devm_request_region(dev, base[id], DIO48E_EXTENT, name)) {
|
|
dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
|
|
base[id], base[id] + DIO48E_EXTENT);
|
|
return -EBUSY;
|
|
}
|
|
|
|
dio48egpio->chip.label = name;
|
|
dio48egpio->chip.parent = dev;
|
|
dio48egpio->chip.owner = THIS_MODULE;
|
|
dio48egpio->chip.base = -1;
|
|
dio48egpio->chip.ngpio = DIO48E_NGPIO;
|
|
dio48egpio->chip.names = dio48e_names;
|
|
dio48egpio->chip.get_direction = dio48e_gpio_get_direction;
|
|
dio48egpio->chip.direction_input = dio48e_gpio_direction_input;
|
|
dio48egpio->chip.direction_output = dio48e_gpio_direction_output;
|
|
dio48egpio->chip.get = dio48e_gpio_get;
|
|
dio48egpio->chip.set = dio48e_gpio_set;
|
|
dio48egpio->chip.set_multiple = dio48e_gpio_set_multiple;
|
|
dio48egpio->base = base[id];
|
|
|
|
raw_spin_lock_init(&dio48egpio->lock);
|
|
|
|
err = devm_gpiochip_add_data(dev, &dio48egpio->chip, dio48egpio);
|
|
if (err) {
|
|
dev_err(dev, "GPIO registering failed (%d)\n", err);
|
|
return err;
|
|
}
|
|
|
|
/* initialize all GPIO as output */
|
|
outb(0x80, base[id] + 3);
|
|
outb(0x00, base[id]);
|
|
outb(0x00, base[id] + 1);
|
|
outb(0x00, base[id] + 2);
|
|
outb(0x00, base[id] + 3);
|
|
outb(0x80, base[id] + 7);
|
|
outb(0x00, base[id] + 4);
|
|
outb(0x00, base[id] + 5);
|
|
outb(0x00, base[id] + 6);
|
|
outb(0x00, base[id] + 7);
|
|
|
|
/* disable IRQ by default */
|
|
inb(base[id] + 0xB);
|
|
|
|
err = gpiochip_irqchip_add(&dio48egpio->chip, &dio48e_irqchip, 0,
|
|
handle_edge_irq, IRQ_TYPE_NONE);
|
|
if (err) {
|
|
dev_err(dev, "Could not add irqchip (%d)\n", err);
|
|
return err;
|
|
}
|
|
|
|
err = devm_request_irq(dev, irq[id], dio48e_irq_handler, 0, name,
|
|
dio48egpio);
|
|
if (err) {
|
|
dev_err(dev, "IRQ handler registering failed (%d)\n", err);
|
|
return err;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct isa_driver dio48e_driver = {
|
|
.probe = dio48e_probe,
|
|
.driver = {
|
|
.name = "104-dio-48e"
|
|
},
|
|
};
|
|
module_isa_driver(dio48e_driver, num_dio48e);
|
|
|
|
MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
|
|
MODULE_DESCRIPTION("ACCES 104-DIO-48E GPIO driver");
|
|
MODULE_LICENSE("GPL v2");
|