For VCN3.0 SRIOV, Guest driver needs to communicate with mmsch to set the World Switch for MM appropriately. This patch add the interface for mmsch_v3.0. Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
		
			
				
	
	
		
			131 lines
		
	
	
		
			3.8 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			131 lines
		
	
	
		
			3.8 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Copyright 2020 Advanced Micro Devices, Inc.
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|  *
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|  * Permission is hereby granted, free of charge, to any person obtaining a
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|  * copy of this software and associated documentation files (the "Software"),
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|  * to deal in the Software without restriction, including without limitation
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|  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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|  * and/or sell copies of the Software, and to permit persons to whom the
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|  * Software is furnished to do so, subject to the following conditions:
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|  *
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|  * The above copyright notice and this permission notice shall be included in
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|  * all copies or substantial portions of the Software.
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|  *
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|  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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|  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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|  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
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|  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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|  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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|  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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|  * OTHER DEALINGS IN THE SOFTWARE.
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|  *
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|  */
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| 
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| #ifndef __MMSCH_V3_0_H__
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| #define __MMSCH_V3_0_H__
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| 
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| #include "amdgpu_vcn.h"
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| 
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| #define MMSCH_VERSION_MAJOR	3
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| #define MMSCH_VERSION_MINOR	0
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| #define MMSCH_VERSION	(MMSCH_VERSION_MAJOR << 16 | MMSCH_VERSION_MINOR)
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| 
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| enum mmsch_v3_0_command_type {
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| 	MMSCH_COMMAND__DIRECT_REG_WRITE = 0,
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| 	MMSCH_COMMAND__DIRECT_REG_POLLING = 2,
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| 	MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE = 3,
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| 	MMSCH_COMMAND__INDIRECT_REG_WRITE = 8,
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| 	MMSCH_COMMAND__END = 0xf
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| };
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| 
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| struct mmsch_v3_0_table_info {
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| 	uint32_t init_status;
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| 	uint32_t table_offset;
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| 	uint32_t table_size;
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| };
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| 
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| struct mmsch_v3_0_init_header {
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| 	uint32_t version;
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| 	uint32_t total_size;
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| 	struct mmsch_v3_0_table_info inst[AMDGPU_MAX_VCN_INSTANCES];
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| };
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| 
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| struct mmsch_v3_0_cmd_direct_reg_header {
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| 	uint32_t reg_offset   : 28;
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| 	uint32_t command_type : 4;
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| };
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| 
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| struct mmsch_v3_0_cmd_indirect_reg_header {
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| 	uint32_t reg_offset    : 20;
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| 	uint32_t reg_idx_space : 8;
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| 	uint32_t command_type  : 4;
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| };
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| 
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| struct mmsch_v3_0_cmd_direct_write {
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| 	struct mmsch_v3_0_cmd_direct_reg_header cmd_header;
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| 	uint32_t reg_value;
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| };
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| 
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| struct mmsch_v3_0_cmd_direct_read_modify_write {
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| 	struct mmsch_v3_0_cmd_direct_reg_header cmd_header;
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| 	uint32_t write_data;
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| 	uint32_t mask_value;
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| };
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| 
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| struct mmsch_v3_0_cmd_direct_polling {
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| 	struct mmsch_v3_0_cmd_direct_reg_header cmd_header;
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| 	uint32_t mask_value;
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| 	uint32_t wait_value;
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| };
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| 
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| struct mmsch_v3_0_cmd_end {
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| 	struct mmsch_v3_0_cmd_direct_reg_header cmd_header;
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| };
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| 
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| struct mmsch_v3_0_cmd_indirect_write {
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| 	struct mmsch_v3_0_cmd_indirect_reg_header cmd_header;
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| 	uint32_t reg_value;
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| };
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| 
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| #define MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \
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| 	size = sizeof(struct mmsch_v3_0_cmd_direct_read_modify_write); \
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| 	size_dw = size / 4; \
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| 	direct_rd_mod_wt.cmd_header.reg_offset = reg; \
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| 	direct_rd_mod_wt.mask_value = mask; \
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| 	direct_rd_mod_wt.write_data = data; \
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| 	memcpy((void *)table_loc, &direct_rd_mod_wt, size); \
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| 	table_loc += size_dw; \
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| 	table_size += size_dw; \
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| }
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| 
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| #define MMSCH_V3_0_INSERT_DIRECT_WT(reg, value) { \
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| 	size = sizeof(struct mmsch_v3_0_cmd_direct_write); \
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| 	size_dw = size / 4; \
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| 	direct_wt.cmd_header.reg_offset = reg; \
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| 	direct_wt.reg_value = value; \
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| 	memcpy((void *)table_loc, &direct_wt, size); \
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| 	table_loc += size_dw; \
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| 	table_size += size_dw; \
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| }
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| 
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| #define MMSCH_V3_0_INSERT_DIRECT_POLL(reg, mask, wait) { \
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| 	size = sizeof(struct mmsch_v3_0_cmd_direct_polling); \
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| 	size_dw = size / 4; \
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| 	direct_poll.cmd_header.reg_offset = reg; \
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| 	direct_poll.mask_value = mask; \
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| 	direct_poll.wait_value = wait; \
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| 	memcpy((void *)table_loc, &direct_poll, size); \
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| 	table_loc += size_dw; \
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| 	table_size += size_dw; \
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| }
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| 
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| #define MMSCH_V3_0_INSERT_END() { \
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| 	size = sizeof(struct mmsch_v3_0_cmd_end); \
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| 	size_dw = size / 4; \
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| 	memcpy((void *)table_loc, &end, size); \
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| 	table_loc += size_dw; \
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| 	table_size += size_dw; \
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| }
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| 
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| #endif
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