forked from Minki/linux
a3905af5be
Include:
- Update for Litex SoC controller to support wider width registers as
well as reset.
- Refactor SMP code to use device tree to define possible cpus.
- Updates build including generating vmlinux.bin
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Merge tag 'for-linus' of git://github.com/openrisc/linux
Pull OpenRISC updates from Stafford Horne:
- Update for Litex SoC controller to support wider width registers as
well as reset.
- Refactor SMP code to use device tree to define possible cpus.
- Update build including generating vmlinux.bin
* tag 'for-linus' of git://github.com/openrisc/linux:
openrisc: Use devicetree to determine present cpus
drivers/soc/litex: Add restart handler
openrisc: add arch/openrisc/Kbuild
drivers/soc/litex: make 'litex_[set|get]_reg()' methods private
drivers/soc/litex: support 32-bit subregisters, 64-bit CPUs
drivers/soc/litex: s/LITEX_REG_SIZE/LITEX_SUBREG_ALIGN/g
drivers/soc/litex: separate MMIO from subregister offset calculation
drivers/soc/litex: move generic accessors to litex.h
openrisc: restart: Call common handlers before hanging
openrisc: Add vmlinux.bin target
33 lines
870 B
Plaintext
33 lines
870 B
Plaintext
# SPDX-License_Identifier: GPL-2.0
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menu "Enable LiteX SoC Builder specific drivers"
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config LITEX
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bool
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config LITEX_SOC_CONTROLLER
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tristate "Enable LiteX SoC Controller driver"
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depends on OF || COMPILE_TEST
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depends on HAS_IOMEM
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select LITEX
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help
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This option enables the SoC Controller Driver which verifies
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LiteX CSR access and provides common litex_[read|write]*
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accessors.
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All drivers that use functions from litex.h must depend on
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LITEX.
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config LITEX_SUBREG_SIZE
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int "Size of a LiteX CSR subregister, in bytes"
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depends on LITEX
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range 1 4
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default 4
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help
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LiteX MMIO registers (referred to as Configuration and Status
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registers, or CSRs) are spread across adjacent 8- or 32-bit
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subregisters, located at 32-bit aligned MMIO addresses. Use
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this to select the appropriate size (1 or 4 bytes) matching
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your particular LiteX build.
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endmenu
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