forked from Minki/linux
70b5c5aae5
This reverts commit a693e050ed.
This breaks on systems with huge amounts of system memory as we do not have
enough vram to store the page tables. Additionally, this is less of an issue
with the recent gtt manager changes.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1106 lines
30 KiB
C
1106 lines
30 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/firmware.h>
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#include "drmP.h"
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#include "amdgpu.h"
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#include "gmc_v6_0.h"
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#include "amdgpu_ucode.h"
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#include "bif/bif_3_0_d.h"
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#include "bif/bif_3_0_sh_mask.h"
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#include "oss/oss_1_0_d.h"
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#include "oss/oss_1_0_sh_mask.h"
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#include "gmc/gmc_6_0_d.h"
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#include "gmc/gmc_6_0_sh_mask.h"
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#include "dce/dce_6_0_d.h"
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#include "dce/dce_6_0_sh_mask.h"
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#include "si_enums.h"
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static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev);
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static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
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static int gmc_v6_0_wait_for_idle(void *handle);
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MODULE_FIRMWARE("radeon/tahiti_mc.bin");
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MODULE_FIRMWARE("radeon/pitcairn_mc.bin");
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MODULE_FIRMWARE("radeon/verde_mc.bin");
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MODULE_FIRMWARE("radeon/oland_mc.bin");
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#define MC_SEQ_MISC0__MT__MASK 0xf0000000
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#define MC_SEQ_MISC0__MT__GDDR1 0x10000000
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#define MC_SEQ_MISC0__MT__DDR2 0x20000000
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#define MC_SEQ_MISC0__MT__GDDR3 0x30000000
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#define MC_SEQ_MISC0__MT__GDDR4 0x40000000
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#define MC_SEQ_MISC0__MT__GDDR5 0x50000000
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#define MC_SEQ_MISC0__MT__HBM 0x60000000
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#define MC_SEQ_MISC0__MT__DDR3 0xB0000000
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static const u32 crtc_offsets[6] =
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{
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SI_CRTC0_REGISTER_OFFSET,
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SI_CRTC1_REGISTER_OFFSET,
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SI_CRTC2_REGISTER_OFFSET,
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SI_CRTC3_REGISTER_OFFSET,
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SI_CRTC4_REGISTER_OFFSET,
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SI_CRTC5_REGISTER_OFFSET
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};
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static void gmc_v6_0_mc_stop(struct amdgpu_device *adev,
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struct amdgpu_mode_mc_save *save)
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{
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u32 blackout;
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if (adev->mode_info.num_crtc)
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amdgpu_display_stop_mc_access(adev, save);
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gmc_v6_0_wait_for_idle((void *)adev);
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blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
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if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
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/* Block CPU access */
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WREG32(mmBIF_FB_EN, 0);
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/* blackout the MC */
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blackout = REG_SET_FIELD(blackout,
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MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
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WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
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}
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/* wait for the MC to settle */
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udelay(100);
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}
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static void gmc_v6_0_mc_resume(struct amdgpu_device *adev,
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struct amdgpu_mode_mc_save *save)
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{
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u32 tmp;
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/* unblackout the MC */
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tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
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tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
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WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
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/* allow CPU access */
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tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
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tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
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WREG32(mmBIF_FB_EN, tmp);
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if (adev->mode_info.num_crtc)
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amdgpu_display_resume_mc_access(adev, save);
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}
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static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
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{
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const char *chip_name;
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char fw_name[30];
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int err;
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DRM_DEBUG("\n");
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switch (adev->asic_type) {
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case CHIP_TAHITI:
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chip_name = "tahiti";
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break;
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case CHIP_PITCAIRN:
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chip_name = "pitcairn";
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break;
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case CHIP_VERDE:
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chip_name = "verde";
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break;
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case CHIP_OLAND:
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chip_name = "oland";
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break;
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case CHIP_HAINAN:
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chip_name = "hainan";
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break;
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default: BUG();
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}
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snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
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err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
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if (err)
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goto out;
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err = amdgpu_ucode_validate(adev->mc.fw);
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out:
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if (err) {
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dev_err(adev->dev,
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"si_mc: Failed to load firmware \"%s\"\n",
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fw_name);
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release_firmware(adev->mc.fw);
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adev->mc.fw = NULL;
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}
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return err;
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}
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static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
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{
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const __le32 *new_fw_data = NULL;
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u32 running;
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const __le32 *new_io_mc_regs = NULL;
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int i, regs_size, ucode_size;
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const struct mc_firmware_header_v1_0 *hdr;
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if (!adev->mc.fw)
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return -EINVAL;
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hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
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amdgpu_ucode_print_mc_hdr(&hdr->header);
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adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
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regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
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new_io_mc_regs = (const __le32 *)
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(adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
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ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
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new_fw_data = (const __le32 *)
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(adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;
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if (running == 0) {
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/* reset the engine and set to writable */
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WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
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WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
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/* load mc io regs */
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for (i = 0; i < regs_size; i++) {
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WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
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WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
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}
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/* load the MC ucode */
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for (i = 0; i < ucode_size; i++) {
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WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
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}
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/* put the engine back into the active state */
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WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
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WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
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WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
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/* wait for training to complete */
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for (i = 0; i < adev->usec_timeout; i++) {
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if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK)
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break;
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udelay(1);
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}
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for (i = 0; i < adev->usec_timeout; i++) {
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if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK)
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break;
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udelay(1);
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}
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}
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return 0;
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}
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static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
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struct amdgpu_mc *mc)
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{
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if (mc->mc_vram_size > 0xFFC0000000ULL) {
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dev_warn(adev->dev, "limiting VRAM\n");
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mc->real_vram_size = 0xFFC0000000ULL;
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mc->mc_vram_size = 0xFFC0000000ULL;
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}
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amdgpu_vram_location(adev, &adev->mc, 0);
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adev->mc.gtt_base_align = 0;
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amdgpu_gtt_location(adev, mc);
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}
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static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
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{
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struct amdgpu_mode_mc_save save;
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u32 tmp;
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int i, j;
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/* Initialize HDP */
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for (i = 0, j = 0; i < 32; i++, j += 0x6) {
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WREG32((0xb05 + j), 0x00000000);
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WREG32((0xb06 + j), 0x00000000);
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WREG32((0xb07 + j), 0x00000000);
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WREG32((0xb08 + j), 0x00000000);
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WREG32((0xb09 + j), 0x00000000);
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}
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WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
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gmc_v6_0_mc_stop(adev, &save);
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if (gmc_v6_0_wait_for_idle((void *)adev)) {
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dev_warn(adev->dev, "Wait for MC idle timedout !\n");
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}
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WREG32(mmVGA_HDP_CONTROL, VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK);
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/* Update configuration */
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WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
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adev->mc.vram_start >> 12);
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WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
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adev->mc.vram_end >> 12);
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WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
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adev->vram_scratch.gpu_addr >> 12);
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tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
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tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
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WREG32(mmMC_VM_FB_LOCATION, tmp);
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/* XXX double check these! */
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WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
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WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
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WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
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WREG32(mmMC_VM_AGP_BASE, 0);
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WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
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WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
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if (gmc_v6_0_wait_for_idle((void *)adev)) {
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dev_warn(adev->dev, "Wait for MC idle timedout !\n");
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}
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gmc_v6_0_mc_resume(adev, &save);
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amdgpu_display_set_vga_render_state(adev, false);
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}
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static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
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{
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u32 tmp;
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int chansize, numchan;
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tmp = RREG32(mmMC_ARB_RAMCFG);
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if (tmp & (1 << 11)) {
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chansize = 16;
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} else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) {
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chansize = 64;
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} else {
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chansize = 32;
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}
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tmp = RREG32(mmMC_SHARED_CHMAP);
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switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
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case 0:
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default:
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numchan = 1;
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break;
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case 1:
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numchan = 2;
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break;
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case 2:
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numchan = 4;
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break;
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case 3:
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numchan = 8;
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break;
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case 4:
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numchan = 3;
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break;
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case 5:
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numchan = 6;
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break;
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case 6:
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numchan = 10;
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break;
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case 7:
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numchan = 12;
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break;
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case 8:
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numchan = 16;
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break;
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}
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adev->mc.vram_width = numchan * chansize;
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/* Could aper size report 0 ? */
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adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
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adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
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/* size in MB on si */
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adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
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adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
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adev->mc.visible_vram_size = adev->mc.aper_size;
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/* unless the user had overridden it, set the gart
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* size equal to the 1024 or vram, whichever is larger.
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*/
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if (amdgpu_gart_size == -1)
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adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
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else
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adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
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gmc_v6_0_vram_gtt_location(adev, &adev->mc);
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return 0;
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}
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static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
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uint32_t vmid)
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{
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WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
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WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
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}
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static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev,
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void *cpu_pt_addr,
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uint32_t gpu_page_idx,
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uint64_t addr,
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uint32_t flags)
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{
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void __iomem *ptr = (void *)cpu_pt_addr;
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uint64_t value;
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value = addr & 0xFFFFFFFFFFFFF000ULL;
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value |= flags;
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writeq(value, ptr + (gpu_page_idx * 8));
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return 0;
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}
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static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
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bool value)
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{
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u32 tmp;
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tmp = RREG32(mmVM_CONTEXT1_CNTL);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
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RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
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DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
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PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
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VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
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READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
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WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
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WREG32(mmVM_CONTEXT1_CNTL, tmp);
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}
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static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
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{
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int r, i;
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if (adev->gart.robj == NULL) {
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dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
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return -EINVAL;
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}
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r = amdgpu_gart_table_vram_pin(adev);
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if (r)
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return r;
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/* Setup TLB control */
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WREG32(mmMC_VM_MX_L1_TLB_CNTL,
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(0xA << 7) |
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MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK |
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MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK |
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MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
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MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK |
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(0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
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/* Setup L2 cache */
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WREG32(mmVM_L2_CNTL,
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VM_L2_CNTL__ENABLE_L2_CACHE_MASK |
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VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK |
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VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
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VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
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(7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
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(1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
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WREG32(mmVM_L2_CNTL2,
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VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK |
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VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK);
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WREG32(mmVM_L2_CNTL3,
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VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
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(4UL << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
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(4UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
|
|
/* setup context0 */
|
|
WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
|
|
WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
|
|
WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
|
|
WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
|
|
(u32)(adev->dummy_page.addr >> 12));
|
|
WREG32(mmVM_CONTEXT0_CNTL2, 0);
|
|
WREG32(mmVM_CONTEXT0_CNTL,
|
|
VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK |
|
|
(0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
|
|
VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
|
|
|
|
WREG32(0x575, 0);
|
|
WREG32(0x576, 0);
|
|
WREG32(0x577, 0);
|
|
|
|
/* empty context1-15 */
|
|
/* set vm size, must be a multiple of 4 */
|
|
WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
|
|
WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
|
|
/* Assign the pt base to something valid for now; the pts used for
|
|
* the VMs are determined by the application and setup and assigned
|
|
* on the fly in the vm part of radeon_gart.c
|
|
*/
|
|
for (i = 1; i < 16; i++) {
|
|
if (i < 8)
|
|
WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
|
|
adev->gart.table_addr >> 12);
|
|
else
|
|
WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
|
|
adev->gart.table_addr >> 12);
|
|
}
|
|
|
|
/* enable context1-15 */
|
|
WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
|
|
(u32)(adev->dummy_page.addr >> 12));
|
|
WREG32(mmVM_CONTEXT1_CNTL2, 4);
|
|
WREG32(mmVM_CONTEXT1_CNTL,
|
|
VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK |
|
|
(1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
|
|
((amdgpu_vm_block_size - 9) << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT) |
|
|
VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
|
|
VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |
|
|
VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
|
|
VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |
|
|
VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
|
|
VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |
|
|
VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
|
|
VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |
|
|
VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
|
|
VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |
|
|
VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
|
|
VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
|
|
|
|
gmc_v6_0_gart_flush_gpu_tlb(adev, 0);
|
|
dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
|
|
(unsigned)(adev->mc.gtt_size >> 20),
|
|
(unsigned long long)adev->gart.table_addr);
|
|
adev->gart.ready = true;
|
|
return 0;
|
|
}
|
|
|
|
static int gmc_v6_0_gart_init(struct amdgpu_device *adev)
|
|
{
|
|
int r;
|
|
|
|
if (adev->gart.robj) {
|
|
dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
|
|
return 0;
|
|
}
|
|
r = amdgpu_gart_init(adev);
|
|
if (r)
|
|
return r;
|
|
adev->gart.table_size = adev->gart.num_gpu_pages * 8;
|
|
return amdgpu_gart_table_vram_alloc(adev);
|
|
}
|
|
|
|
static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)
|
|
{
|
|
/*unsigned i;
|
|
|
|
for (i = 1; i < 16; ++i) {
|
|
uint32_t reg;
|
|
if (i < 8)
|
|
reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ;
|
|
else
|
|
reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8);
|
|
adev->vm_manager.saved_table_addr[i] = RREG32(reg);
|
|
}*/
|
|
|
|
/* Disable all tables */
|
|
WREG32(mmVM_CONTEXT0_CNTL, 0);
|
|
WREG32(mmVM_CONTEXT1_CNTL, 0);
|
|
/* Setup TLB control */
|
|
WREG32(mmMC_VM_MX_L1_TLB_CNTL,
|
|
MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
|
|
(0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
|
|
/* Setup L2 cache */
|
|
WREG32(mmVM_L2_CNTL,
|
|
VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
|
|
VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
|
|
(7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
|
|
(1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
|
|
WREG32(mmVM_L2_CNTL2, 0);
|
|
WREG32(mmVM_L2_CNTL3,
|
|
VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
|
|
(0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
|
|
amdgpu_gart_table_vram_unpin(adev);
|
|
}
|
|
|
|
static void gmc_v6_0_gart_fini(struct amdgpu_device *adev)
|
|
{
|
|
amdgpu_gart_table_vram_free(adev);
|
|
amdgpu_gart_fini(adev);
|
|
}
|
|
|
|
static int gmc_v6_0_vm_init(struct amdgpu_device *adev)
|
|
{
|
|
/*
|
|
* number of VMs
|
|
* VMID 0 is reserved for System
|
|
* amdgpu graphics/compute will use VMIDs 1-7
|
|
* amdkfd will use VMIDs 8-15
|
|
*/
|
|
adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
|
|
amdgpu_vm_manager_init(adev);
|
|
|
|
/* base offset of vram pages */
|
|
if (adev->flags & AMD_IS_APU) {
|
|
u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
|
|
tmp <<= 22;
|
|
adev->vm_manager.vram_base_offset = tmp;
|
|
} else
|
|
adev->vm_manager.vram_base_offset = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void gmc_v6_0_vm_fini(struct amdgpu_device *adev)
|
|
{
|
|
}
|
|
|
|
static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
|
|
u32 status, u32 addr, u32 mc_client)
|
|
{
|
|
u32 mc_id;
|
|
u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
|
|
u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
|
|
PROTECTIONS);
|
|
char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
|
|
(mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
|
|
|
|
mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
|
|
MEMORY_CLIENT_ID);
|
|
|
|
dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
|
|
protections, vmid, addr,
|
|
REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
|
|
MEMORY_CLIENT_RW) ?
|
|
"write" : "read", block, mc_client, mc_id);
|
|
}
|
|
|
|
/*
|
|
static const u32 mc_cg_registers[] = {
|
|
MC_HUB_MISC_HUB_CG,
|
|
MC_HUB_MISC_SIP_CG,
|
|
MC_HUB_MISC_VM_CG,
|
|
MC_XPB_CLK_GAT,
|
|
ATC_MISC_CG,
|
|
MC_CITF_MISC_WR_CG,
|
|
MC_CITF_MISC_RD_CG,
|
|
MC_CITF_MISC_VM_CG,
|
|
VM_L2_CG,
|
|
};
|
|
|
|
static const u32 mc_cg_ls_en[] = {
|
|
MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
|
|
MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
|
|
MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
|
|
MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
|
|
ATC_MISC_CG__MEM_LS_ENABLE_MASK,
|
|
MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
|
|
MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
|
|
MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
|
|
VM_L2_CG__MEM_LS_ENABLE_MASK,
|
|
};
|
|
|
|
static const u32 mc_cg_en[] = {
|
|
MC_HUB_MISC_HUB_CG__ENABLE_MASK,
|
|
MC_HUB_MISC_SIP_CG__ENABLE_MASK,
|
|
MC_HUB_MISC_VM_CG__ENABLE_MASK,
|
|
MC_XPB_CLK_GAT__ENABLE_MASK,
|
|
ATC_MISC_CG__ENABLE_MASK,
|
|
MC_CITF_MISC_WR_CG__ENABLE_MASK,
|
|
MC_CITF_MISC_RD_CG__ENABLE_MASK,
|
|
MC_CITF_MISC_VM_CG__ENABLE_MASK,
|
|
VM_L2_CG__ENABLE_MASK,
|
|
};
|
|
|
|
static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev,
|
|
bool enable)
|
|
{
|
|
int i;
|
|
u32 orig, data;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
|
|
orig = data = RREG32(mc_cg_registers[i]);
|
|
if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
|
|
data |= mc_cg_ls_en[i];
|
|
else
|
|
data &= ~mc_cg_ls_en[i];
|
|
if (data != orig)
|
|
WREG32(mc_cg_registers[i], data);
|
|
}
|
|
}
|
|
|
|
static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev,
|
|
bool enable)
|
|
{
|
|
int i;
|
|
u32 orig, data;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
|
|
orig = data = RREG32(mc_cg_registers[i]);
|
|
if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
|
|
data |= mc_cg_en[i];
|
|
else
|
|
data &= ~mc_cg_en[i];
|
|
if (data != orig)
|
|
WREG32(mc_cg_registers[i], data);
|
|
}
|
|
}
|
|
|
|
static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev,
|
|
bool enable)
|
|
{
|
|
u32 orig, data;
|
|
|
|
orig = data = RREG32_PCIE(ixPCIE_CNTL2);
|
|
|
|
if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
|
|
data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
|
|
data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
|
|
data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
|
|
data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
|
|
} else {
|
|
data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
|
|
data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
|
|
data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
|
|
data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
|
|
}
|
|
|
|
if (orig != data)
|
|
WREG32_PCIE(ixPCIE_CNTL2, data);
|
|
}
|
|
|
|
static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
|
|
bool enable)
|
|
{
|
|
u32 orig, data;
|
|
|
|
orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
|
|
|
|
if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
|
|
data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
|
|
else
|
|
data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
|
|
|
|
if (orig != data)
|
|
WREG32(mmHDP_HOST_PATH_CNTL, data);
|
|
}
|
|
|
|
static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
|
|
bool enable)
|
|
{
|
|
u32 orig, data;
|
|
|
|
orig = data = RREG32(mmHDP_MEM_POWER_LS);
|
|
|
|
if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
|
|
data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
|
|
else
|
|
data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
|
|
|
|
if (orig != data)
|
|
WREG32(mmHDP_MEM_POWER_LS, data);
|
|
}
|
|
*/
|
|
|
|
static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type)
|
|
{
|
|
switch (mc_seq_vram_type) {
|
|
case MC_SEQ_MISC0__MT__GDDR1:
|
|
return AMDGPU_VRAM_TYPE_GDDR1;
|
|
case MC_SEQ_MISC0__MT__DDR2:
|
|
return AMDGPU_VRAM_TYPE_DDR2;
|
|
case MC_SEQ_MISC0__MT__GDDR3:
|
|
return AMDGPU_VRAM_TYPE_GDDR3;
|
|
case MC_SEQ_MISC0__MT__GDDR4:
|
|
return AMDGPU_VRAM_TYPE_GDDR4;
|
|
case MC_SEQ_MISC0__MT__GDDR5:
|
|
return AMDGPU_VRAM_TYPE_GDDR5;
|
|
case MC_SEQ_MISC0__MT__DDR3:
|
|
return AMDGPU_VRAM_TYPE_DDR3;
|
|
default:
|
|
return AMDGPU_VRAM_TYPE_UNKNOWN;
|
|
}
|
|
}
|
|
|
|
static int gmc_v6_0_early_init(void *handle)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
gmc_v6_0_set_gart_funcs(adev);
|
|
gmc_v6_0_set_irq_funcs(adev);
|
|
|
|
if (adev->flags & AMD_IS_APU) {
|
|
adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
|
|
} else {
|
|
u32 tmp = RREG32(mmMC_SEQ_MISC0);
|
|
tmp &= MC_SEQ_MISC0__MT__MASK;
|
|
adev->mc.vram_type = gmc_v6_0_convert_vram_type(tmp);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gmc_v6_0_late_init(void *handle)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
|
|
}
|
|
|
|
static int gmc_v6_0_sw_init(void *handle)
|
|
{
|
|
int r;
|
|
int dma_bits;
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
|
|
if (r)
|
|
return r;
|
|
|
|
r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
|
|
if (r)
|
|
return r;
|
|
|
|
adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
|
|
|
|
adev->mc.mc_mask = 0xffffffffffULL;
|
|
|
|
adev->need_dma32 = false;
|
|
dma_bits = adev->need_dma32 ? 32 : 40;
|
|
r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
|
|
if (r) {
|
|
adev->need_dma32 = true;
|
|
dma_bits = 32;
|
|
dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
|
|
}
|
|
r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
|
|
if (r) {
|
|
pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
|
|
dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n");
|
|
}
|
|
|
|
r = gmc_v6_0_init_microcode(adev);
|
|
if (r) {
|
|
dev_err(adev->dev, "Failed to load mc firmware!\n");
|
|
return r;
|
|
}
|
|
|
|
r = gmc_v6_0_mc_init(adev);
|
|
if (r)
|
|
return r;
|
|
|
|
r = amdgpu_bo_init(adev);
|
|
if (r)
|
|
return r;
|
|
|
|
r = gmc_v6_0_gart_init(adev);
|
|
if (r)
|
|
return r;
|
|
|
|
if (!adev->vm_manager.enabled) {
|
|
r = gmc_v6_0_vm_init(adev);
|
|
if (r) {
|
|
dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
|
|
return r;
|
|
}
|
|
adev->vm_manager.enabled = true;
|
|
}
|
|
|
|
return r;
|
|
}
|
|
|
|
static int gmc_v6_0_sw_fini(void *handle)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
if (adev->vm_manager.enabled) {
|
|
gmc_v6_0_vm_fini(adev);
|
|
adev->vm_manager.enabled = false;
|
|
}
|
|
gmc_v6_0_gart_fini(adev);
|
|
amdgpu_gem_force_release(adev);
|
|
amdgpu_bo_fini(adev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gmc_v6_0_hw_init(void *handle)
|
|
{
|
|
int r;
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
gmc_v6_0_mc_program(adev);
|
|
|
|
if (!(adev->flags & AMD_IS_APU)) {
|
|
r = gmc_v6_0_mc_load_microcode(adev);
|
|
if (r) {
|
|
dev_err(adev->dev, "Failed to load MC firmware!\n");
|
|
return r;
|
|
}
|
|
}
|
|
|
|
r = gmc_v6_0_gart_enable(adev);
|
|
if (r)
|
|
return r;
|
|
|
|
return r;
|
|
}
|
|
|
|
static int gmc_v6_0_hw_fini(void *handle)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
|
|
gmc_v6_0_gart_disable(adev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gmc_v6_0_suspend(void *handle)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
if (adev->vm_manager.enabled) {
|
|
gmc_v6_0_vm_fini(adev);
|
|
adev->vm_manager.enabled = false;
|
|
}
|
|
gmc_v6_0_hw_fini(adev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gmc_v6_0_resume(void *handle)
|
|
{
|
|
int r;
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
r = gmc_v6_0_hw_init(adev);
|
|
if (r)
|
|
return r;
|
|
|
|
if (!adev->vm_manager.enabled) {
|
|
r = gmc_v6_0_vm_init(adev);
|
|
if (r) {
|
|
dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
|
|
return r;
|
|
}
|
|
adev->vm_manager.enabled = true;
|
|
}
|
|
|
|
return r;
|
|
}
|
|
|
|
static bool gmc_v6_0_is_idle(void *handle)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
u32 tmp = RREG32(mmSRBM_STATUS);
|
|
|
|
if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
|
|
SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
static int gmc_v6_0_wait_for_idle(void *handle)
|
|
{
|
|
unsigned i;
|
|
u32 tmp;
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
for (i = 0; i < adev->usec_timeout; i++) {
|
|
tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
|
|
SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
|
|
SRBM_STATUS__MCC_BUSY_MASK |
|
|
SRBM_STATUS__MCD_BUSY_MASK |
|
|
SRBM_STATUS__VMC_BUSY_MASK);
|
|
if (!tmp)
|
|
return 0;
|
|
udelay(1);
|
|
}
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
static int gmc_v6_0_soft_reset(void *handle)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
struct amdgpu_mode_mc_save save;
|
|
u32 srbm_soft_reset = 0;
|
|
u32 tmp = RREG32(mmSRBM_STATUS);
|
|
|
|
if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
|
|
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
|
|
SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
|
|
|
|
if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
|
|
SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
|
|
if (!(adev->flags & AMD_IS_APU))
|
|
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
|
|
SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
|
|
}
|
|
|
|
if (srbm_soft_reset) {
|
|
gmc_v6_0_mc_stop(adev, &save);
|
|
if (gmc_v6_0_wait_for_idle(adev)) {
|
|
dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
|
|
}
|
|
|
|
|
|
tmp = RREG32(mmSRBM_SOFT_RESET);
|
|
tmp |= srbm_soft_reset;
|
|
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
|
|
WREG32(mmSRBM_SOFT_RESET, tmp);
|
|
tmp = RREG32(mmSRBM_SOFT_RESET);
|
|
|
|
udelay(50);
|
|
|
|
tmp &= ~srbm_soft_reset;
|
|
WREG32(mmSRBM_SOFT_RESET, tmp);
|
|
tmp = RREG32(mmSRBM_SOFT_RESET);
|
|
|
|
udelay(50);
|
|
|
|
gmc_v6_0_mc_resume(adev, &save);
|
|
udelay(50);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
|
|
struct amdgpu_irq_src *src,
|
|
unsigned type,
|
|
enum amdgpu_interrupt_state state)
|
|
{
|
|
u32 tmp;
|
|
u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
|
|
VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
|
|
VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
|
|
VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
|
|
VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
|
|
VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
|
|
|
|
switch (state) {
|
|
case AMDGPU_IRQ_STATE_DISABLE:
|
|
tmp = RREG32(mmVM_CONTEXT0_CNTL);
|
|
tmp &= ~bits;
|
|
WREG32(mmVM_CONTEXT0_CNTL, tmp);
|
|
tmp = RREG32(mmVM_CONTEXT1_CNTL);
|
|
tmp &= ~bits;
|
|
WREG32(mmVM_CONTEXT1_CNTL, tmp);
|
|
break;
|
|
case AMDGPU_IRQ_STATE_ENABLE:
|
|
tmp = RREG32(mmVM_CONTEXT0_CNTL);
|
|
tmp |= bits;
|
|
WREG32(mmVM_CONTEXT0_CNTL, tmp);
|
|
tmp = RREG32(mmVM_CONTEXT1_CNTL);
|
|
tmp |= bits;
|
|
WREG32(mmVM_CONTEXT1_CNTL, tmp);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
|
|
struct amdgpu_irq_src *source,
|
|
struct amdgpu_iv_entry *entry)
|
|
{
|
|
u32 addr, status;
|
|
|
|
addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
|
|
status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
|
|
WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
|
|
|
|
if (!addr && !status)
|
|
return 0;
|
|
|
|
if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
|
|
gmc_v6_0_set_fault_enable_default(adev, false);
|
|
|
|
if (printk_ratelimit()) {
|
|
dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
|
|
entry->src_id, entry->src_data);
|
|
dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
|
|
addr);
|
|
dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
|
|
status);
|
|
gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gmc_v6_0_set_clockgating_state(void *handle,
|
|
enum amd_clockgating_state state)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int gmc_v6_0_set_powergating_state(void *handle,
|
|
enum amd_powergating_state state)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
|
|
.name = "gmc_v6_0",
|
|
.early_init = gmc_v6_0_early_init,
|
|
.late_init = gmc_v6_0_late_init,
|
|
.sw_init = gmc_v6_0_sw_init,
|
|
.sw_fini = gmc_v6_0_sw_fini,
|
|
.hw_init = gmc_v6_0_hw_init,
|
|
.hw_fini = gmc_v6_0_hw_fini,
|
|
.suspend = gmc_v6_0_suspend,
|
|
.resume = gmc_v6_0_resume,
|
|
.is_idle = gmc_v6_0_is_idle,
|
|
.wait_for_idle = gmc_v6_0_wait_for_idle,
|
|
.soft_reset = gmc_v6_0_soft_reset,
|
|
.set_clockgating_state = gmc_v6_0_set_clockgating_state,
|
|
.set_powergating_state = gmc_v6_0_set_powergating_state,
|
|
};
|
|
|
|
static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = {
|
|
.flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb,
|
|
.set_pte_pde = gmc_v6_0_gart_set_pte_pde,
|
|
};
|
|
|
|
static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
|
|
.set = gmc_v6_0_vm_fault_interrupt_state,
|
|
.process = gmc_v6_0_process_interrupt,
|
|
};
|
|
|
|
static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev)
|
|
{
|
|
if (adev->gart.gart_funcs == NULL)
|
|
adev->gart.gart_funcs = &gmc_v6_0_gart_funcs;
|
|
}
|
|
|
|
static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
|
|
{
|
|
adev->mc.vm_fault.num_types = 1;
|
|
adev->mc.vm_fault.funcs = &gmc_v6_0_irq_funcs;
|
|
}
|
|
|
|
const struct amdgpu_ip_block_version gmc_v6_0_ip_block =
|
|
{
|
|
.type = AMD_IP_BLOCK_TYPE_GMC,
|
|
.major = 6,
|
|
.minor = 0,
|
|
.rev = 0,
|
|
.funcs = &gmc_v6_0_ip_funcs,
|
|
};
|