forked from Minki/linux
83a21727c3
Since SCLK, MISO and MOSI are the only mandatory signals at Zynq's SPI
interfaces, SS0, SS1 and SS2 have to be configured separately as they may
be used as simple GPIO lines.
This, of course, has to be considered in the devicetree, so pin controller
configuration for e.g. an SPI0 using SS0 and SS1 only might look like the
following snippet (derived from the example of chapter "17.5.3
MIO/EMIO" Routing of Zynq-7000 TRM UG585). So MIO20 can now be used
as GPIO instead of being occupied by SPI0 SS2 function. Note the separate
pinmux function for the slave select signals:
pinctrl_spi0_default: spi0-default {
mux_spi {
function = "spi0";
groups = "spi0_0_grp";
};
mux_ss {
function = "spi0_ss";
groups = "spi0_0_ss0_grp", "spi0_0_ss1_grp";
}
conf-output {
pins = "MIO16", "MIO21";
slew-rate = <0>;
bias-disable;
low-power-disable;
io-standard = <1>;
};
conf-input {
pins = "MIO17";
slew-rate = <0>;
bias-high-impedance;
low-power-disable;
io-standard = <1>;
};
conf-select {
pins = "MIO18", "MIO19";
slew-rate = <0>;
bias-pull-up;
low-power-disable;
io-standard = <1>;
};
};
pinctrl_gpio0_default {
mux {
function = "gpio0";
groups = "gpio0_20_grp"
};
conf {
pins = "MIO20";
slew-rate = <0>;
bias-pull-up;
low-power-disable;
io-standard = <1>;
};
};
Signed-off-by: Helmut Buchsbaum <helmut.buchsbaum@gmail.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
106 lines
3.5 KiB
Plaintext
106 lines
3.5 KiB
Plaintext
Binding for Xilinx Zynq Pinctrl
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Required properties:
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- compatible: "xlnx,zynq-pinctrl"
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- syscon: phandle to SLCR
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- reg: Offset and length of pinctrl space in SLCR
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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Zynq's pin configuration nodes act as a container for an arbitrary number of
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subnodes. Each of these subnodes represents some desired configuration for a
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pin, a group, or a list of pins or groups. This configuration can include the
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mux function to select on those pin(s)/group(s), and various pin configuration
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parameters, such as pull-up, slew rate, etc.
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Each configuration node can consist of multiple nodes describing the pinmux and
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pinconf options. Those nodes can be pinmux nodes or pinconf nodes.
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The name of each subnode is not important; all subnodes should be enumerated
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and processed purely based on their content.
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Required properties for pinmux nodes are:
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- groups: A list of pinmux groups.
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- function: The name of a pinmux function to activate for the specified set
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of groups.
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Required properties for configuration nodes:
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One of:
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- pins: a list of pin names
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- groups: A list of pinmux groups.
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The following generic properties as defined in pinctrl-bindings.txt are valid
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to specify in a pinmux subnode:
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groups, function
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The following generic properties as defined in pinctrl-bindings.txt are valid
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to specify in a pinconf subnode:
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groups, pins, bias-disable, bias-high-impedance, bias-pull-up, slew-rate,
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low-power-disable, low-power-enable
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Valid arguments for 'slew-rate' are '0' and '1' to select between slow and fast
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respectively.
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Valid values for groups are:
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ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp, mdio1_0_grp,
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qspi0_0_grp, qspi1_0_grp, qspi_fbclk, qspi_cs1_grp, spi0_0_grp - spi0_2_grp,
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spi0_X_ssY (X=0..2, Y=0..2), spi1_0_grp - spi1_3_grp,
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spi1_X_ssY (X=0..3, Y=0..2), sdio0_0_grp - sdio0_2_grp,
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sdio1_0_grp - sdio1_3_grp, sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp,
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sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp, smc0_nor_addr25_grp, smc0_nand,
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can0_0_grp - can0_10_grp, can1_0_grp - can1_11_grp, uart0_0_grp - uart0_10_grp,
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uart1_0_grp - uart1_11_grp, i2c0_0_grp - i2c0_10_grp, i2c1_0_grp - i2c1_10_grp,
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ttc0_0_grp - ttc0_2_grp, ttc1_0_grp - ttc1_2_grp, swdt0_0_grp - swdt0_4_grp,
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gpio0_0_grp - gpio0_53_grp, usb0_0_grp, usb1_0_grp
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Valid values for pins are:
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MIO0 - MIO53
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Valid values for function are:
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ethernet0, ethernet1, mdio0, mdio1, qspi0, qspi1, qspi_fbclk, qspi_cs1,
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spi0, spi0_ss, spi1, spi1_ss, sdio0, sdio0_pc, sdio0_cd, sdio0_wp,
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sdio1, sdio1_pc, sdio1_cd, sdio1_wp,
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smc0_nor, smc0_nor_cs1, smc0_nor_addr25, smc0_nand, can0, can1, uart0, uart1,
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i2c0, i2c1, ttc0, ttc1, swdt0, gpio0, usb0, usb1
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The following driver-specific properties as defined here are valid to specify in
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a pin configuration subnode:
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- io-standard: Configure the pin to use the selected IO standard according to
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this mapping:
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1: LVCMOS18
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2: LVCMOS25
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3: LVCMOS33
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4: HSTL
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Example:
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pinctrl0: pinctrl@700 {
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compatible = "xlnx,pinctrl-zynq";
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reg = <0x700 0x200>;
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syscon = <&slcr>;
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pinctrl_uart1_default: uart1-default {
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mux {
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groups = "uart1_10_grp";
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function = "uart1";
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};
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conf {
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groups = "uart1_10_grp";
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slew-rate = <0>;
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io-standard = <1>;
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};
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conf-rx {
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pins = "MIO49";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO48";
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bias-disable;
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};
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};
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};
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