forked from Minki/linux
9d778f0c5f
According to the databook ep0 should be in setup phase during reset. If host issues reset between control transfers, ep0 will be in an invalid state. Fix this by issuing stall and restart on ep0 if it is not in setup phase. Also SW needs to complete pending control transfer and setup core for next setup stage as per data book. Hence check ep0 state during reset interrupt handling and make sure active transfers on ep0 out/in endpoint are stopped by queuing ENDXFER command for that endpoint and restart ep0 out again to receive next setup packet. Signed-off-by: Mayank Rana <quic_mrana@quicinc.com> Link: https://lore.kernel.org/r/1651693001-29891-1-git-send-email-quic_mrana@quicinc.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
153 lines
5.0 KiB
C
153 lines
5.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* gadget.h - DesignWare USB3 DRD Gadget Header
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
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*
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* Authors: Felipe Balbi <balbi@ti.com>,
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* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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*/
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#ifndef __DRIVERS_USB_DWC3_GADGET_H
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#define __DRIVERS_USB_DWC3_GADGET_H
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#include <linux/list.h>
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#include <linux/usb/gadget.h>
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#include "io.h"
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struct dwc3;
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#define to_dwc3_ep(ep) (container_of(ep, struct dwc3_ep, endpoint))
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#define gadget_to_dwc(g) (dev_get_platdata(&g->dev))
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/* DEPCFG parameter 1 */
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#define DWC3_DEPCFG_INT_NUM(n) (((n) & 0x1f) << 0)
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#define DWC3_DEPCFG_XFER_COMPLETE_EN BIT(8)
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#define DWC3_DEPCFG_XFER_IN_PROGRESS_EN BIT(9)
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#define DWC3_DEPCFG_XFER_NOT_READY_EN BIT(10)
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#define DWC3_DEPCFG_FIFO_ERROR_EN BIT(11)
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#define DWC3_DEPCFG_STREAM_EVENT_EN BIT(13)
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#define DWC3_DEPCFG_BINTERVAL_M1(n) (((n) & 0xff) << 16)
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#define DWC3_DEPCFG_STREAM_CAPABLE BIT(24)
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#define DWC3_DEPCFG_EP_NUMBER(n) (((n) & 0x1f) << 25)
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#define DWC3_DEPCFG_BULK_BASED BIT(30)
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#define DWC3_DEPCFG_FIFO_BASED BIT(31)
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/* DEPCFG parameter 0 */
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#define DWC3_DEPCFG_EP_TYPE(n) (((n) & 0x3) << 1)
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#define DWC3_DEPCFG_MAX_PACKET_SIZE(n) (((n) & 0x7ff) << 3)
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#define DWC3_DEPCFG_FIFO_NUMBER(n) (((n) & 0x1f) << 17)
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#define DWC3_DEPCFG_BURST_SIZE(n) (((n) & 0xf) << 22)
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#define DWC3_DEPCFG_DATA_SEQ_NUM(n) ((n) << 26)
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/* This applies for core versions earlier than 1.94a */
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#define DWC3_DEPCFG_IGN_SEQ_NUM BIT(31)
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/* These apply for core versions 1.94a and later */
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#define DWC3_DEPCFG_ACTION_INIT (0 << 30)
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#define DWC3_DEPCFG_ACTION_RESTORE BIT(30)
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#define DWC3_DEPCFG_ACTION_MODIFY (2 << 30)
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/* DEPXFERCFG parameter 0 */
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#define DWC3_DEPXFERCFG_NUM_XFER_RES(n) ((n) & 0xffff)
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/* U1 Device exit Latency */
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#define DWC3_DEFAULT_U1_DEV_EXIT_LAT 0x0A /* Less then 10 microsec */
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/* U2 Device exit Latency */
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#define DWC3_DEFAULT_U2_DEV_EXIT_LAT 0x1FF /* Less then 511 microsec */
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/* Frame/Microframe Number Mask */
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#define DWC3_FRNUMBER_MASK 0x3fff
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/* -------------------------------------------------------------------------- */
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#define to_dwc3_request(r) (container_of(r, struct dwc3_request, request))
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/**
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* next_request - gets the next request on the given list
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* @list: the request list to operate on
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*
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* Caller should take care of locking. This function return %NULL or the first
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* request available on @list.
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*/
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static inline struct dwc3_request *next_request(struct list_head *list)
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{
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return list_first_entry_or_null(list, struct dwc3_request, list);
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}
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/**
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* dwc3_gadget_move_started_request - move @req to the started_list
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* @req: the request to be moved
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*
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* Caller should take care of locking. This function will move @req from its
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* current list to the endpoint's started_list.
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*/
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static inline void dwc3_gadget_move_started_request(struct dwc3_request *req)
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{
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struct dwc3_ep *dep = req->dep;
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req->status = DWC3_REQUEST_STATUS_STARTED;
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list_move_tail(&req->list, &dep->started_list);
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}
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/**
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* dwc3_gadget_move_cancelled_request - move @req to the cancelled_list
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* @req: the request to be moved
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* @reason: cancelled reason for the dwc3 request
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*
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* Caller should take care of locking. This function will move @req from its
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* current list to the endpoint's cancelled_list.
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*/
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static inline void dwc3_gadget_move_cancelled_request(struct dwc3_request *req,
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unsigned int reason)
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{
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struct dwc3_ep *dep = req->dep;
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req->status = reason;
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list_move_tail(&req->list, &dep->cancelled_list);
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}
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void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
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int status);
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void dwc3_ep0_interrupt(struct dwc3 *dwc,
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const struct dwc3_event_depevt *event);
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void dwc3_ep0_out_start(struct dwc3 *dwc);
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void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep);
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void dwc3_ep0_stall_and_restart(struct dwc3 *dwc);
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int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value);
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int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value);
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int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
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gfp_t gfp_flags);
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int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol);
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void dwc3_ep0_send_delayed_status(struct dwc3 *dwc);
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void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, bool interrupt);
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/**
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* dwc3_gadget_ep_get_transfer_index - Gets transfer index from HW
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* @dep: dwc3 endpoint
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*
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* Caller should take care of locking. Returns the transfer resource
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* index for a given endpoint.
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*/
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static inline void dwc3_gadget_ep_get_transfer_index(struct dwc3_ep *dep)
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{
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u32 res_id;
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res_id = dwc3_readl(dep->regs, DWC3_DEPCMD);
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dep->resource_index = DWC3_DEPCMD_GET_RSC_IDX(res_id);
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}
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/**
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* dwc3_gadget_dctl_write_safe - write to DCTL safe from link state change
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* @dwc: pointer to our context structure
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* @value: value to write to DCTL
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*
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* Use this function when doing read-modify-write to DCTL. It will not
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* send link state change request.
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*/
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static inline void dwc3_gadget_dctl_write_safe(struct dwc3 *dwc, u32 value)
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{
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value &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
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dwc3_writel(dwc->regs, DWC3_DCTL, value);
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}
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#endif /* __DRIVERS_USB_DWC3_GADGET_H */
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