forked from Minki/linux
2874c5fd28
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
166 lines
3.4 KiB
C
166 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* misc setup functions for MPC83xx
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*
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* Maintainer: Kumar Gala <galak@kernel.crashing.org>
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/of_platform.h>
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#include <linux/pci.h>
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#include <asm/debug.h>
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#include <asm/io.h>
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#include <asm/hw_irq.h>
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#include <asm/ipic.h>
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#include <soc/fsl/qe/qe_ic.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include "mpc83xx.h"
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static __be32 __iomem *restart_reg_base;
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static int __init mpc83xx_restart_init(void)
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{
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/* map reset restart_reg_baseister space */
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restart_reg_base = ioremap(get_immrbase() + 0x900, 0xff);
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return 0;
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}
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arch_initcall(mpc83xx_restart_init);
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void __noreturn mpc83xx_restart(char *cmd)
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{
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#define RST_OFFSET 0x00000900
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#define RST_PROT_REG 0x00000018
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#define RST_CTRL_REG 0x0000001c
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local_irq_disable();
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if (restart_reg_base) {
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/* enable software reset "RSTE" */
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out_be32(restart_reg_base + (RST_PROT_REG >> 2), 0x52535445);
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/* set software hard reset */
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out_be32(restart_reg_base + (RST_CTRL_REG >> 2), 0x2);
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} else {
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printk (KERN_EMERG "Error: Restart registers not mapped, spinning!\n");
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}
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for (;;) ;
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}
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long __init mpc83xx_time_init(void)
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{
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#define SPCR_OFFSET 0x00000110
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#define SPCR_TBEN 0x00400000
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__be32 __iomem *spcr = ioremap(get_immrbase() + SPCR_OFFSET, 4);
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__be32 tmp;
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tmp = in_be32(spcr);
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out_be32(spcr, tmp | SPCR_TBEN);
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iounmap(spcr);
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return 0;
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}
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void __init mpc83xx_ipic_init_IRQ(void)
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{
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struct device_node *np;
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/* looking for fsl,pq2pro-pic which is asl compatible with fsl,ipic */
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np = of_find_compatible_node(NULL, NULL, "fsl,ipic");
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if (!np)
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np = of_find_node_by_type(NULL, "ipic");
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if (!np)
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return;
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ipic_init(np, 0);
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of_node_put(np);
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/* Initialize the default interrupt mapping priorities,
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* in case the boot rom changed something on us.
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*/
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ipic_set_default_priority();
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}
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#ifdef CONFIG_QUICC_ENGINE
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void __init mpc83xx_qe_init_IRQ(void)
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{
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struct device_node *np;
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np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
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if (!np) {
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np = of_find_node_by_type(NULL, "qeic");
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if (!np)
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return;
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}
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qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
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of_node_put(np);
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}
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void __init mpc83xx_ipic_and_qe_init_IRQ(void)
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{
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mpc83xx_ipic_init_IRQ();
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mpc83xx_qe_init_IRQ();
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}
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#endif /* CONFIG_QUICC_ENGINE */
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static const struct of_device_id of_bus_ids[] __initconst = {
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{ .type = "soc", },
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{ .compatible = "soc", },
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{ .compatible = "simple-bus" },
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{ .compatible = "gianfar" },
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{ .compatible = "gpio-leds", },
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{ .type = "qe", },
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{ .compatible = "fsl,qe", },
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{},
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};
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int __init mpc83xx_declare_of_platform_devices(void)
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{
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of_platform_bus_probe(NULL, of_bus_ids, NULL);
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return 0;
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}
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#ifdef CONFIG_PCI
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void __init mpc83xx_setup_pci(void)
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{
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struct device_node *np;
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for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
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mpc83xx_add_bridge(np);
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for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie")
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mpc83xx_add_bridge(np);
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}
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#endif
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void __init mpc83xx_setup_arch(void)
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{
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if (ppc_md.progress)
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ppc_md.progress("mpc83xx_setup_arch()", 0);
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mpc83xx_setup_pci();
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}
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int machine_check_83xx(struct pt_regs *regs)
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{
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u32 mask = 1 << (31 - IPIC_MCP_WDT);
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if (!(regs->msr & SRR1_MCE_MCP) || !(ipic_get_mcp_status() & mask))
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return machine_check_generic(regs);
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ipic_clear_mcp_status(mask);
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if (debugger_fault_handler(regs))
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return 1;
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die("Watchdog NMI Reset", regs, 0);
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return 1;
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}
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