2874c5fd28
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
125 lines
3.6 KiB
C
125 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>
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*
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* Loongson 1 MUX Register Definitions.
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*/
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#ifndef __ASM_MACH_LOONGSON32_REGS_MUX_H
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#define __ASM_MACH_LOONGSON32_REGS_MUX_H
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#define LS1X_MUX_REG(x) \
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((void __iomem *)KSEG1ADDR(LS1X_MUX_BASE + (x)))
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#define LS1X_MUX_CTRL0 LS1X_MUX_REG(0x0)
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#define LS1X_MUX_CTRL1 LS1X_MUX_REG(0x4)
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#if defined(CONFIG_LOONGSON1_LS1B)
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/* MUX CTRL0 Register Bits */
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#define UART0_USE_PWM23 BIT(28)
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#define UART0_USE_PWM01 BIT(27)
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#define UART1_USE_LCD0_5_6_11 BIT(26)
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#define I2C2_USE_CAN1 BIT(25)
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#define I2C1_USE_CAN0 BIT(24)
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#define NAND3_USE_UART5 BIT(23)
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#define NAND3_USE_UART4 BIT(22)
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#define NAND3_USE_UART1_DAT BIT(21)
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#define NAND3_USE_UART1_CTS BIT(20)
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#define NAND3_USE_PWM23 BIT(19)
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#define NAND3_USE_PWM01 BIT(18)
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#define NAND2_USE_UART5 BIT(17)
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#define NAND2_USE_UART4 BIT(16)
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#define NAND2_USE_UART1_DAT BIT(15)
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#define NAND2_USE_UART1_CTS BIT(14)
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#define NAND2_USE_PWM23 BIT(13)
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#define NAND2_USE_PWM01 BIT(12)
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#define NAND1_USE_UART5 BIT(11)
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#define NAND1_USE_UART4 BIT(10)
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#define NAND1_USE_UART1_DAT BIT(9)
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#define NAND1_USE_UART1_CTS BIT(8)
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#define NAND1_USE_PWM23 BIT(7)
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#define NAND1_USE_PWM01 BIT(6)
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#define GMAC1_USE_UART1 BIT(4)
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#define GMAC1_USE_UART0 BIT(3)
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#define LCD_USE_UART0_DAT BIT(2)
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#define LCD_USE_UART15 BIT(1)
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#define LCD_USE_UART0 BIT(0)
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/* MUX CTRL1 Register Bits */
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#define USB_RESET BIT(31)
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#define SPI1_CS_USE_PWM01 BIT(24)
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#define SPI1_USE_CAN BIT(23)
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#define DISABLE_DDR_CONFSPACE BIT(20)
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#define DDR32TO16EN BIT(16)
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#define GMAC1_SHUT BIT(13)
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#define GMAC0_SHUT BIT(12)
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#define USB_SHUT BIT(11)
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#define UART1_3_USE_CAN1 BIT(5)
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#define UART1_2_USE_CAN0 BIT(4)
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#define GMAC1_USE_TXCLK BIT(3)
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#define GMAC0_USE_TXCLK BIT(2)
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#define GMAC1_USE_PWM23 BIT(1)
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#define GMAC0_USE_PWM01 BIT(0)
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#elif defined(CONFIG_LOONGSON1_LS1C)
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/* SHUT_CTRL Register Bits */
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#define UART_SPLIT GENMASK(31, 30)
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#define OUTPUT_CLK GENMASK(29, 26)
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#define ADC_SHUT BIT(25)
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#define SDIO_SHUT BIT(24)
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#define DMA2_SHUT BIT(23)
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#define DMA1_SHUT BIT(22)
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#define DMA0_SHUT BIT(21)
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#define SPI1_SHUT BIT(20)
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#define SPI0_SHUT BIT(19)
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#define I2C2_SHUT BIT(18)
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#define I2C1_SHUT BIT(17)
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#define I2C0_SHUT BIT(16)
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#define AC97_SHUT BIT(15)
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#define I2S_SHUT BIT(14)
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#define UART3_SHUT BIT(13)
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#define UART2_SHUT BIT(12)
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#define UART1_SHUT BIT(11)
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#define UART0_SHUT BIT(10)
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#define CAN1_SHUT BIT(9)
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#define CAN0_SHUT BIT(8)
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#define ECC_SHUT BIT(7)
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#define GMAC_SHUT BIT(6)
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#define USBHOST_SHUT BIT(5)
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#define USBOTG_SHUT BIT(4)
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#define SDRAM_SHUT BIT(3)
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#define SRAM_SHUT BIT(2)
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#define CAM_SHUT BIT(1)
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#define LCD_SHUT BIT(0)
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#define UART_SPLIT_SHIFT 30
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#define OUTPUT_CLK_SHIFT 26
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/* MISC_CTRL Register Bits */
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#define USBHOST_RSTN BIT(31)
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#define PHY_INTF_SELI GENMASK(30, 28)
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#define AC97_EN BIT(25)
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#define SDIO_DMA_EN GENMASK(24, 23)
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#define ADC_DMA_EN BIT(22)
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#define SDIO_USE_SPI1 BIT(17)
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#define SDIO_USE_SPI0 BIT(16)
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#define SRAM_CTRL GENMASK(15, 0)
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#define PHY_INTF_SELI_SHIFT 28
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#define SDIO_DMA_EN_SHIFT 23
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#define SRAM_CTRL_SHIFT 0
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#define LS1X_CBUS_REG(n, x) \
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((void __iomem *)KSEG1ADDR(LS1X_CBUS_BASE + (n * 0x04) + (x)))
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#define LS1X_CBUS_FIRST(n) LS1X_CBUS_REG(n, 0x00)
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#define LS1X_CBUS_SECOND(n) LS1X_CBUS_REG(n, 0x10)
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#define LS1X_CBUS_THIRD(n) LS1X_CBUS_REG(n, 0x20)
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#define LS1X_CBUS_FOURTHT(n) LS1X_CBUS_REG(n, 0x30)
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#define LS1X_CBUS_FIFTHT(n) LS1X_CBUS_REG(n, 0x40)
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#endif
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#endif /* __ASM_MACH_LOONGSON32_REGS_MUX_H */
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