d203c2d3ee
This is an add-on patch to the main SoC Sparx5 series (Message-ID: <20200513125532.24585-1-lars.povlsen@microchip.com>). This changes the miim pinctrl function name from "miim1" to "miim" due to refactoring in the driver, obsoleting the instance number. The change in the driver was to better fit new platforms, as the instance number is redundant information. Specifically, support for the Microchip Sparx5 SoC is being submitted, where this change became necessary. Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
266 lines
5.1 KiB
Plaintext
266 lines
5.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2017 Microsemi Corporation */
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mscc,ocelot";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "mips,mips24KEc";
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device_type = "cpu";
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clocks = <&cpu_clk>;
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reg = <0>;
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};
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};
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aliases {
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serial0 = &uart0;
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};
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cpuintc: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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cpu_clk: cpu-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <500000000>;
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};
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ahb_clk: ahb-clk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clocks = <&cpu_clk>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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ahb@70000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x70000000 0x2000000>;
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interrupt-parent = <&intc>;
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cpu_ctrl: syscon@0 {
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compatible = "mscc,ocelot-cpu-syscon", "syscon";
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reg = <0x0 0x2c>;
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};
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intc: interrupt-controller@70 {
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compatible = "mscc,ocelot-icpu-intr";
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reg = <0x70 0x70>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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};
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uart0: serial@100000 {
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pinctrl-0 = <&uart_pins>;
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pinctrl-names = "default";
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compatible = "ns16550a";
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reg = <0x100000 0x20>;
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interrupts = <6>;
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clocks = <&ahb_clk>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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i2c: i2c@100400 {
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compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
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pinctrl-0 = <&i2c_pins>;
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pinctrl-names = "default";
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reg = <0x100400 0x100>, <0x198 0x8>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <8>;
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clocks = <&ahb_clk>;
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status = "disabled";
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};
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uart2: serial@100800 {
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pinctrl-0 = <&uart2_pins>;
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pinctrl-names = "default";
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compatible = "ns16550a";
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reg = <0x100800 0x20>;
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interrupts = <7>;
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clocks = <&ahb_clk>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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spi: spi@101000 {
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compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x101000 0x100>, <0x3c 0x18>;
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interrupts = <9>;
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clocks = <&ahb_clk>;
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status = "disabled";
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};
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switch@1010000 {
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compatible = "mscc,vsc7514-switch";
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reg = <0x1010000 0x10000>,
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<0x1030000 0x10000>,
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<0x1080000 0x100>,
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<0x10e0000 0x10000>,
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<0x11e0000 0x100>,
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<0x11f0000 0x100>,
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<0x1200000 0x100>,
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<0x1210000 0x100>,
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<0x1220000 0x100>,
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<0x1230000 0x100>,
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<0x1240000 0x100>,
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<0x1250000 0x100>,
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<0x1260000 0x100>,
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<0x1270000 0x100>,
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<0x1280000 0x100>,
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<0x1800000 0x80000>,
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<0x1880000 0x10000>,
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<0x1060000 0x10000>;
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reg-names = "sys", "rew", "qs", "ptp", "port0", "port1",
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"port2", "port3", "port4", "port5", "port6",
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"port7", "port8", "port9", "port10", "qsys",
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"ana", "s2";
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interrupts = <18 21 22>;
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interrupt-names = "ptp_rdy", "xtr", "inj";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port0: port@0 {
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reg = <0>;
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};
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port1: port@1 {
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reg = <1>;
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};
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port2: port@2 {
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reg = <2>;
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};
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port3: port@3 {
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reg = <3>;
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};
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port4: port@4 {
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reg = <4>;
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};
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port5: port@5 {
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reg = <5>;
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};
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port6: port@6 {
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reg = <6>;
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};
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port7: port@7 {
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reg = <7>;
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};
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port8: port@8 {
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reg = <8>;
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};
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port9: port@9 {
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reg = <9>;
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};
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port10: port@10 {
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reg = <10>;
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};
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};
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};
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reset@1070008 {
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compatible = "mscc,ocelot-chip-reset";
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reg = <0x1070008 0x4>;
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};
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gpio: pinctrl@1070034 {
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compatible = "mscc,ocelot-pinctrl";
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reg = <0x1070034 0x68>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&gpio 0 0 22>;
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interrupt-controller;
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interrupts = <13>;
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#interrupt-cells = <2>;
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i2c_pins: i2c-pins {
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pins = "GPIO_16", "GPIO_17";
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function = "twi";
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};
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uart_pins: uart-pins {
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pins = "GPIO_6", "GPIO_7";
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function = "uart";
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};
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uart2_pins: uart2-pins {
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pins = "GPIO_12", "GPIO_13";
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function = "uart2";
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};
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miim1: miim1 {
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pins = "GPIO_14", "GPIO_15";
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function = "miim";
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};
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};
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mdio0: mdio@107009c {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mscc,ocelot-miim";
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reg = <0x107009c 0x24>, <0x10700f0 0x8>;
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interrupts = <14>;
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status = "disabled";
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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phy2: ethernet-phy@2 {
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reg = <2>;
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};
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phy3: ethernet-phy@3 {
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reg = <3>;
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};
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};
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mdio1: mdio@10700c0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mscc,ocelot-miim";
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reg = <0x10700c0 0x24>;
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interrupts = <15>;
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pinctrl-names = "default";
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pinctrl-0 = <&miim1>;
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status = "disabled";
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};
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hsio: syscon@10d0000 {
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compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
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reg = <0x10d0000 0x10000>;
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serdes: serdes {
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compatible = "mscc,vsc7514-serdes";
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#phy-cells = <2>;
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};
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};
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};
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};
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