forked from Minki/linux
88b2b32bab
* Convert {ide_hwif_t,ide_pci_device_t}->host_flag to be u16.
* Add IDE_HFLAG_POST_SET_MODE host flag to indicate the need to program
the host for the transfer mode after programming the device. Set it
in au1xxx-ide, amd74xx, cs5530, cs5535, pdc202xx_new, sc1200, pmac
and via82cxxx host drivers.
* Add IDE_HFLAG_NO_SET_MODE host flag to indicate the need to completely
skip programming of host/device for the transfer mode ("smart" hosts).
Set it in it821x host driver and check it in ide_tune_dma().
* Add ide_set_pio_mode()/ide_set_dma_mode() helpers and convert all
direct ->set_pio_mode/->speedproc users to use these helpers.
* Move ide_config_drive_speed() calls from ->set_pio_mode/->speedproc
methods to callers.
* Rename ->speedproc method to ->set_dma_mode, make it void and update
all implementations accordingly.
* Update ide_set_xfer_rate() comments.
* Unexport ide_config_drive_speed().
v2:
* Fix issues noticed by Sergei:
- export ide_set_dma_mode() instead of moving ->set_pio_mode abuse wrt
to setting DMA modes from sc1200_set_pio_mode() to do_special()
- check IDE_HFLAG_NO_SET_MODE in ide_tune_dma()
- check for (hwif->set_pio_mode) == NULL in ide_set_pio_mode()
- check for (hwif->set_dma_mode) == NULL in ide_set_dma_mode()
- return -1 from ide_set_{pio,dma}_mode() if ->set_{pio,dma}_mode == NULL
- don't set ->set_{pio,dma}_mode on it821x in "smart" mode
- fix build problem in pmac.c
- minor fixes in au1xxx-ide.c/cs5530.c/siimage.c
- improve patch description
Changes in behavior caused by this patch:
- HDIO_SET_PIO_MODE ioctl would now return -ENOSYS for attempts to change
PIO mode if it821x controller is in "smart" mode
- removal of two debugging printk-s (from cs5530.c and sc1200.c)
- transfer modes 0x00-0x07 passed from user space may be programmed twice on
the device (not really an issue since 0x00 is not supported correctly by
any host driver ATM, 0x01 is not supported at all and 0x02-0x07 are invalid)
Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
332 lines
8.1 KiB
C
332 lines
8.1 KiB
C
/*
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* linux/drivers/ide/pci/atiixp.c Version 0.02 Jun 16 2007
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*
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* Copyright (C) 2003 ATI Inc. <hyu@ati.com>
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* Copyright (C) 2004,2007 Bartlomiej Zolnierkiewicz
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*/
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/ioport.h>
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#include <linux/pci.h>
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#include <linux/hdreg.h>
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#include <linux/ide.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <asm/io.h>
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#define ATIIXP_IDE_PIO_TIMING 0x40
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#define ATIIXP_IDE_MDMA_TIMING 0x44
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#define ATIIXP_IDE_PIO_CONTROL 0x48
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#define ATIIXP_IDE_PIO_MODE 0x4a
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#define ATIIXP_IDE_UDMA_CONTROL 0x54
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#define ATIIXP_IDE_UDMA_MODE 0x56
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typedef struct {
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u8 command_width;
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u8 recover_width;
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} atiixp_ide_timing;
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static atiixp_ide_timing pio_timing[] = {
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{ 0x05, 0x0d },
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{ 0x04, 0x07 },
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{ 0x03, 0x04 },
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{ 0x02, 0x02 },
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{ 0x02, 0x00 },
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};
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static atiixp_ide_timing mdma_timing[] = {
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{ 0x07, 0x07 },
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{ 0x02, 0x01 },
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{ 0x02, 0x00 },
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};
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static int save_mdma_mode[4];
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static DEFINE_SPINLOCK(atiixp_lock);
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/**
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* atiixp_dma_2_pio - return the PIO mode matching DMA
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* @xfer_rate: transfer speed
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*
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* Returns the nearest equivalent PIO timing for the PIO or DMA
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* mode requested by the controller.
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*/
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static u8 atiixp_dma_2_pio(u8 xfer_rate) {
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switch(xfer_rate) {
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case XFER_UDMA_6:
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case XFER_UDMA_5:
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case XFER_UDMA_4:
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case XFER_UDMA_3:
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case XFER_UDMA_2:
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case XFER_UDMA_1:
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case XFER_UDMA_0:
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case XFER_MW_DMA_2:
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case XFER_PIO_4:
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return 4;
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case XFER_MW_DMA_1:
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case XFER_PIO_3:
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return 3;
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case XFER_SW_DMA_2:
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case XFER_PIO_2:
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return 2;
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case XFER_MW_DMA_0:
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case XFER_SW_DMA_1:
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case XFER_SW_DMA_0:
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case XFER_PIO_1:
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case XFER_PIO_0:
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case XFER_PIO_SLOW:
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default:
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return 0;
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}
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}
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static void atiixp_dma_host_on(ide_drive_t *drive)
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{
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struct pci_dev *dev = drive->hwif->pci_dev;
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unsigned long flags;
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u16 tmp16;
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spin_lock_irqsave(&atiixp_lock, flags);
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pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
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if (save_mdma_mode[drive->dn])
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tmp16 &= ~(1 << drive->dn);
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else
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tmp16 |= (1 << drive->dn);
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pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
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spin_unlock_irqrestore(&atiixp_lock, flags);
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ide_dma_host_on(drive);
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}
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static void atiixp_dma_host_off(ide_drive_t *drive)
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{
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struct pci_dev *dev = drive->hwif->pci_dev;
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unsigned long flags;
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u16 tmp16;
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spin_lock_irqsave(&atiixp_lock, flags);
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pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
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tmp16 &= ~(1 << drive->dn);
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pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
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spin_unlock_irqrestore(&atiixp_lock, flags);
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ide_dma_host_off(drive);
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}
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/**
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* atiixp_set_pio_mode - set host controller for PIO mode
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* @drive: drive
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* @pio: PIO mode number
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*
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* Set the interface PIO mode.
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*/
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static void atiixp_set_pio_mode(ide_drive_t *drive, const u8 pio)
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{
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struct pci_dev *dev = drive->hwif->pci_dev;
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unsigned long flags;
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int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
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u32 pio_timing_data;
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u16 pio_mode_data;
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spin_lock_irqsave(&atiixp_lock, flags);
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pci_read_config_word(dev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
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pio_mode_data &= ~(0x07 << (drive->dn * 4));
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pio_mode_data |= (pio << (drive->dn * 4));
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pci_write_config_word(dev, ATIIXP_IDE_PIO_MODE, pio_mode_data);
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pci_read_config_dword(dev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
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pio_timing_data &= ~(0xff << timing_shift);
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pio_timing_data |= (pio_timing[pio].recover_width << timing_shift) |
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(pio_timing[pio].command_width << (timing_shift + 4));
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pci_write_config_dword(dev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);
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spin_unlock_irqrestore(&atiixp_lock, flags);
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}
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/**
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* atiixp_set_dma_mode - set host controller for DMA mode
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* @drive: drive
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* @speed: DMA mode
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*
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* Set a ATIIXP host controller to the desired DMA mode. This involves
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* programming the right timing data into the PCI configuration space.
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*/
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static void atiixp_set_dma_mode(ide_drive_t *drive, const u8 speed)
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{
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struct pci_dev *dev = drive->hwif->pci_dev;
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unsigned long flags;
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int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
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u32 tmp32;
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u16 tmp16;
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u8 pio;
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spin_lock_irqsave(&atiixp_lock, flags);
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save_mdma_mode[drive->dn] = 0;
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if (speed >= XFER_UDMA_0) {
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pci_read_config_word(dev, ATIIXP_IDE_UDMA_MODE, &tmp16);
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tmp16 &= ~(0x07 << (drive->dn * 4));
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tmp16 |= ((speed & 0x07) << (drive->dn * 4));
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pci_write_config_word(dev, ATIIXP_IDE_UDMA_MODE, tmp16);
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} else {
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if ((speed >= XFER_MW_DMA_0) && (speed <= XFER_MW_DMA_2)) {
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save_mdma_mode[drive->dn] = speed;
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pci_read_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, &tmp32);
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tmp32 &= ~(0xff << timing_shift);
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tmp32 |= (mdma_timing[speed & 0x03].recover_width << timing_shift) |
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(mdma_timing[speed & 0x03].command_width << (timing_shift + 4));
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pci_write_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, tmp32);
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}
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}
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spin_unlock_irqrestore(&atiixp_lock, flags);
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if (speed >= XFER_SW_DMA_0)
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pio = atiixp_dma_2_pio(speed);
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else
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pio = speed - XFER_PIO_0;
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atiixp_set_pio_mode(drive, pio);
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}
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/**
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* atiixp_dma_check - set up an IDE device
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* @drive: IDE drive to configure
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*
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* Set up the ATIIXP interface for the best available speed on this
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* interface, preferring DMA to PIO.
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*/
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static int atiixp_dma_check(ide_drive_t *drive)
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{
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drive->init_speed = 0;
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if (ide_tune_dma(drive))
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return 0;
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if (ide_use_fast_pio(drive))
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ide_set_max_pio(drive);
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return -1;
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}
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/**
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* init_hwif_atiixp - fill in the hwif for the ATIIXP
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* @hwif: IDE interface
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*
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* Set up the ide_hwif_t for the ATIIXP interface according to the
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* capabilities of the hardware.
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*/
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static void __devinit init_hwif_atiixp(ide_hwif_t *hwif)
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{
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u8 udma_mode = 0;
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u8 ch = hwif->channel;
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struct pci_dev *pdev = hwif->pci_dev;
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if (!hwif->irq)
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hwif->irq = ch ? 15 : 14;
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hwif->autodma = 0;
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hwif->set_pio_mode = &atiixp_set_pio_mode;
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hwif->set_dma_mode = &atiixp_set_dma_mode;
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hwif->drives[0].autotune = 1;
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hwif->drives[1].autotune = 1;
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if (!hwif->dma_base)
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return;
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hwif->atapi_dma = 1;
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hwif->ultra_mask = 0x3f;
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hwif->mwdma_mask = 0x06;
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hwif->swdma_mask = 0x04;
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pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ch, &udma_mode);
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if ((udma_mode & 0x07) >= 0x04 || (udma_mode & 0x70) >= 0x40)
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hwif->cbl = ATA_CBL_PATA80;
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else
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hwif->cbl = ATA_CBL_PATA40;
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hwif->dma_host_on = &atiixp_dma_host_on;
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hwif->dma_host_off = &atiixp_dma_host_off;
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hwif->ide_dma_check = &atiixp_dma_check;
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if (!noautodma)
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hwif->autodma = 1;
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hwif->drives[1].autodma = hwif->autodma;
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hwif->drives[0].autodma = hwif->autodma;
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}
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static ide_pci_device_t atiixp_pci_info[] __devinitdata = {
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{ /* 0 */
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.name = "ATIIXP",
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.init_hwif = init_hwif_atiixp,
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.autodma = AUTODMA,
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.enablebits = {{0x48,0x01,0x00}, {0x48,0x08,0x00}},
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.bootable = ON_BOARD,
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.pio_mask = ATA_PIO4,
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},{ /* 1 */
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.name = "SB600_PATA",
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.init_hwif = init_hwif_atiixp,
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.autodma = AUTODMA,
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.enablebits = {{0x48,0x01,0x00}, {0x00,0x00,0x00}},
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.bootable = ON_BOARD,
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.host_flags = IDE_HFLAG_SINGLE,
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.pio_mask = ATA_PIO4,
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},
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};
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/**
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* atiixp_init_one - called when a ATIIXP is found
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* @dev: the atiixp device
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* @id: the matching pci id
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*
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* Called when the PCI registration layer (or the IDE initialization)
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* finds a device matching our IDE device tables.
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*/
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static int __devinit atiixp_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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return ide_setup_pci_device(dev, &atiixp_pci_info[id->driver_data]);
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}
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static struct pci_device_id atiixp_pci_tbl[] = {
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{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
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{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
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{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
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{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
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{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, atiixp_pci_tbl);
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static struct pci_driver driver = {
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.name = "ATIIXP_IDE",
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.id_table = atiixp_pci_tbl,
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.probe = atiixp_init_one,
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};
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static int __init atiixp_ide_init(void)
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{
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return ide_pci_register_driver(&driver);
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}
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module_init(atiixp_ide_init);
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MODULE_AUTHOR("HUI YU");
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MODULE_DESCRIPTION("PCI driver module for ATI IXP IDE");
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MODULE_LICENSE("GPL");
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