Daniel Jurgens b47bd6ea40 {net, ib}/mlx5: Make cache line size determination at runtime. ... ARM 64B cache line systems have L1_CACHE_BYTES set to 128. cache_line_size() will return the correct size. Fixes: cf50b5efa2fe('net/mlx5_core/ib: New device capabilities handling.') Signed-off-by: Daniel Jurgens <danielj@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>		2016-10-29 12:00:39 -04:00
..
core	Merge of primary rdma-core code for 4.9	2016-10-09 17:04:33 -07:00
hw	{net, ib}/mlx5: Make cache line size determination at runtime.	2016-10-29 12:00:39 -04:00
sw	kthread: kthread worker API cleanup	2016-10-11 15:06:33 -07:00
ulp	IB/ipoib: move back IB LL address into the hard header	2016-10-14 10:54:53 -04:00
Kconfig	IB/hns: Kconfig and Makefile for RoCE module	2016-08-22 14:02:33 -04:00
Makefile	IB/rdmavt: Create module framework and handle driver registration	2016-03-10 20:37:04 -05:00