bc05aa6e13
The SH7786 has different physical memory layout configurations, configurable through the MMSELR register. The configuration is typically defined by the bootloader, so Linux generally doesn't care. Except that depending on the configuration, some PCI MEM areas may or may not be available. This commit adds a helper function that allows to retrieve the current physical memory layout configuration. It will be used in a following patch to exclude unusable PCI MEM areas during the PCI initialization. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Rich Felker <dalias@libc.org>
142 lines
3.7 KiB
C
142 lines
3.7 KiB
C
/*
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* SH7786 Pinmux
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*
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* Copyright (C) 2008, 2009 Renesas Solutions Corp.
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* Kuninori Morimoto <morimoto.kuninori@renesas.com>
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*
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* Based on sh7785.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __CPU_SH7786_H__
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#define __CPU_SH7786_H__
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#include <linux/io.h>
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enum {
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/* PA */
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GPIO_PA7, GPIO_PA6, GPIO_PA5, GPIO_PA4,
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GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0,
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/* PB */
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GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4,
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GPIO_PB3, GPIO_PB2, GPIO_PB1, GPIO_PB0,
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/* PC */
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GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4,
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GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0,
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/* PD */
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GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4,
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GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0,
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/* PE */
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GPIO_PE7, GPIO_PE6,
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/* PF */
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GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4,
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GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0,
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/* PG */
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GPIO_PG7, GPIO_PG6, GPIO_PG5,
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/* PH */
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GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4,
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GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,
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/* PJ */
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GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4,
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GPIO_PJ3, GPIO_PJ2, GPIO_PJ1,
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/* DU */
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GPIO_FN_DCLKIN, GPIO_FN_DCLKOUT, GPIO_FN_ODDF,
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GPIO_FN_VSYNC, GPIO_FN_HSYNC, GPIO_FN_CDE, GPIO_FN_DISP,
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GPIO_FN_DR0, GPIO_FN_DG0, GPIO_FN_DB0,
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GPIO_FN_DR1, GPIO_FN_DG1, GPIO_FN_DB1,
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GPIO_FN_DR2, GPIO_FN_DG2, GPIO_FN_DB2,
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GPIO_FN_DR3, GPIO_FN_DG3, GPIO_FN_DB3,
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GPIO_FN_DR4, GPIO_FN_DG4, GPIO_FN_DB4,
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GPIO_FN_DR5, GPIO_FN_DG5, GPIO_FN_DB5,
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/* Eth */
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GPIO_FN_ETH_MAGIC, GPIO_FN_ETH_LINK, GPIO_FN_ETH_TX_ER,
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GPIO_FN_ETH_TX_EN, GPIO_FN_ETH_MDIO, GPIO_FN_ETH_RX_CLK,
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GPIO_FN_ETH_MDC, GPIO_FN_ETH_COL, GPIO_FN_ETH_TX_CLK,
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GPIO_FN_ETH_CRS, GPIO_FN_ETH_RX_DV, GPIO_FN_ETH_RX_ER,
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GPIO_FN_ETH_TXD3, GPIO_FN_ETH_TXD2, GPIO_FN_ETH_TXD1, GPIO_FN_ETH_TXD0,
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GPIO_FN_ETH_RXD3, GPIO_FN_ETH_RXD2, GPIO_FN_ETH_RXD1, GPIO_FN_ETH_RXD0,
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/* HSPI */
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GPIO_FN_HSPI_CLK, GPIO_FN_HSPI_CS, GPIO_FN_HSPI_RX, GPIO_FN_HSPI_TX,
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/* SCIF0 */
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GPIO_FN_SCIF0_CTS, GPIO_FN_SCIF0_RTS, GPIO_FN_SCIF0_SCK,
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GPIO_FN_SCIF0_RXD, GPIO_FN_SCIF0_TXD,
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/* SCIF1 */
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GPIO_FN_SCIF1_SCK, GPIO_FN_SCIF1_RXD, GPIO_FN_SCIF1_TXD,
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/* SCIF3 */
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GPIO_FN_SCIF3_SCK, GPIO_FN_SCIF3_RXD, GPIO_FN_SCIF3_TXD,
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/* SCIF4 */
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GPIO_FN_SCIF4_SCK, GPIO_FN_SCIF4_RXD, GPIO_FN_SCIF4_TXD,
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/* SCIF5 */
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GPIO_FN_SCIF5_SCK, GPIO_FN_SCIF5_RXD, GPIO_FN_SCIF5_TXD,
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/* LBSC */
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GPIO_FN_BREQ, GPIO_FN_IOIS16, GPIO_FN_CE2B, GPIO_FN_CE2A, GPIO_FN_BACK,
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/* FLCTL */
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GPIO_FN_FALE, GPIO_FN_FRB, GPIO_FN_FSTATUS,
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GPIO_FN_FSE, GPIO_FN_FCLE,
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/* DMAC */
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GPIO_FN_DACK0, GPIO_FN_DREQ0, GPIO_FN_DRAK0,
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GPIO_FN_DACK1, GPIO_FN_DREQ1, GPIO_FN_DRAK1,
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GPIO_FN_DACK2, GPIO_FN_DREQ2, GPIO_FN_DRAK2,
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GPIO_FN_DACK3, GPIO_FN_DREQ3, GPIO_FN_DRAK3,
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/* USB */
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GPIO_FN_USB_OVC0, GPIO_FN_USB_PENC0,
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GPIO_FN_USB_OVC1, GPIO_FN_USB_PENC1,
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/* HAC */
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GPIO_FN_HAC_RES,
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GPIO_FN_HAC0_SDOUT, GPIO_FN_HAC0_SDIN,
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GPIO_FN_HAC0_SYNC, GPIO_FN_HAC0_BITCLK,
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GPIO_FN_HAC1_SDOUT, GPIO_FN_HAC1_SDIN,
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GPIO_FN_HAC1_SYNC, GPIO_FN_HAC1_BITCLK,
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/* SSI */
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GPIO_FN_SSI0_SDATA, GPIO_FN_SSI0_SCK, GPIO_FN_SSI0_WS, GPIO_FN_SSI0_CLK,
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GPIO_FN_SSI1_SDATA, GPIO_FN_SSI1_SCK, GPIO_FN_SSI1_WS, GPIO_FN_SSI1_CLK,
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GPIO_FN_SSI2_SDATA, GPIO_FN_SSI2_SCK, GPIO_FN_SSI2_WS,
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GPIO_FN_SSI3_SDATA, GPIO_FN_SSI3_SCK, GPIO_FN_SSI3_WS,
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/* SDIF1 */
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GPIO_FN_SDIF1CMD, GPIO_FN_SDIF1CD, GPIO_FN_SDIF1WP, GPIO_FN_SDIF1CLK,
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GPIO_FN_SDIF1D3, GPIO_FN_SDIF1D2, GPIO_FN_SDIF1D1, GPIO_FN_SDIF1D0,
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/* SDIF0 */
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GPIO_FN_SDIF0CMD, GPIO_FN_SDIF0CD, GPIO_FN_SDIF0WP, GPIO_FN_SDIF0CLK,
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GPIO_FN_SDIF0D3, GPIO_FN_SDIF0D2, GPIO_FN_SDIF0D1, GPIO_FN_SDIF0D0,
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/* TMU */
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GPIO_FN_TCLK,
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/* INTC */
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GPIO_FN_IRL7, GPIO_FN_IRL6, GPIO_FN_IRL5, GPIO_FN_IRL4,
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};
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static inline u32 sh7786_mm_sel(void)
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{
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return __raw_readl(0xFC400020) & 0x7;
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}
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#endif /* __CPU_SH7786_H__ */
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