forked from Minki/linux
b445f62377
The mcp23x17_regmap is initialised with structs named "mcp23x16".
However, the mcp23s08 driver doesn't support the MCP23016 device yet, so
this appears to be a typo.
Fixes: 8f38910ba4 ("pinctrl: mcp23s08: switch to regmap caching")
Signed-off-by: Thomas Preston <thomas.preston@codethink.co.uk>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20200828213226.1734264-2-thomas.preston@codethink.co.uk
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
645 lines
17 KiB
C
645 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* MCP23S08 SPI/I2C GPIO driver */
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#include <linux/bitops.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/mutex.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/export.h>
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#include <linux/gpio/driver.h>
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#include <linux/slab.h>
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#include <asm/byteorder.h>
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#include <linux/interrupt.h>
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#include <linux/regmap.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include "pinctrl-mcp23s08.h"
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/* Registers are all 8 bits wide.
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*
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* The mcp23s17 has twice as many bits, and can be configured to work
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* with either 16 bit registers or with two adjacent 8 bit banks.
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*/
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#define MCP_IODIR 0x00 /* init/reset: all ones */
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#define MCP_IPOL 0x01
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#define MCP_GPINTEN 0x02
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#define MCP_DEFVAL 0x03
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#define MCP_INTCON 0x04
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#define MCP_IOCON 0x05
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# define IOCON_MIRROR (1 << 6)
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# define IOCON_SEQOP (1 << 5)
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# define IOCON_HAEN (1 << 3)
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# define IOCON_ODR (1 << 2)
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# define IOCON_INTPOL (1 << 1)
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# define IOCON_INTCC (1)
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#define MCP_GPPU 0x06
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#define MCP_INTF 0x07
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#define MCP_INTCAP 0x08
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#define MCP_GPIO 0x09
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#define MCP_OLAT 0x0a
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static const struct reg_default mcp23x08_defaults[] = {
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{.reg = MCP_IODIR, .def = 0xff},
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{.reg = MCP_IPOL, .def = 0x00},
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{.reg = MCP_GPINTEN, .def = 0x00},
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{.reg = MCP_DEFVAL, .def = 0x00},
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{.reg = MCP_INTCON, .def = 0x00},
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{.reg = MCP_IOCON, .def = 0x00},
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{.reg = MCP_GPPU, .def = 0x00},
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{.reg = MCP_OLAT, .def = 0x00},
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};
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static const struct regmap_range mcp23x08_volatile_range = {
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.range_min = MCP_INTF,
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.range_max = MCP_GPIO,
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};
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static const struct regmap_access_table mcp23x08_volatile_table = {
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.yes_ranges = &mcp23x08_volatile_range,
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.n_yes_ranges = 1,
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};
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static const struct regmap_range mcp23x08_precious_range = {
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.range_min = MCP_GPIO,
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.range_max = MCP_GPIO,
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};
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static const struct regmap_access_table mcp23x08_precious_table = {
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.yes_ranges = &mcp23x08_precious_range,
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.n_yes_ranges = 1,
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};
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const struct regmap_config mcp23x08_regmap = {
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.reg_bits = 8,
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.val_bits = 8,
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.reg_stride = 1,
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.volatile_table = &mcp23x08_volatile_table,
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.precious_table = &mcp23x08_precious_table,
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.reg_defaults = mcp23x08_defaults,
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.num_reg_defaults = ARRAY_SIZE(mcp23x08_defaults),
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.cache_type = REGCACHE_FLAT,
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.max_register = MCP_OLAT,
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};
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EXPORT_SYMBOL_GPL(mcp23x08_regmap);
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static const struct reg_default mcp23x17_defaults[] = {
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{.reg = MCP_IODIR << 1, .def = 0xffff},
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{.reg = MCP_IPOL << 1, .def = 0x0000},
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{.reg = MCP_GPINTEN << 1, .def = 0x0000},
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{.reg = MCP_DEFVAL << 1, .def = 0x0000},
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{.reg = MCP_INTCON << 1, .def = 0x0000},
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{.reg = MCP_IOCON << 1, .def = 0x0000},
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{.reg = MCP_GPPU << 1, .def = 0x0000},
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{.reg = MCP_OLAT << 1, .def = 0x0000},
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};
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static const struct regmap_range mcp23x17_volatile_range = {
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.range_min = MCP_INTF << 1,
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.range_max = MCP_GPIO << 1,
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};
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static const struct regmap_access_table mcp23x17_volatile_table = {
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.yes_ranges = &mcp23x17_volatile_range,
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.n_yes_ranges = 1,
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};
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static const struct regmap_range mcp23x17_precious_range = {
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.range_min = MCP_GPIO << 1,
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.range_max = MCP_GPIO << 1,
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};
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static const struct regmap_access_table mcp23x17_precious_table = {
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.yes_ranges = &mcp23x17_precious_range,
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.n_yes_ranges = 1,
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};
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const struct regmap_config mcp23x17_regmap = {
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.reg_bits = 8,
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.val_bits = 16,
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.reg_stride = 2,
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.max_register = MCP_OLAT << 1,
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.volatile_table = &mcp23x17_volatile_table,
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.precious_table = &mcp23x17_precious_table,
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.reg_defaults = mcp23x17_defaults,
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.num_reg_defaults = ARRAY_SIZE(mcp23x17_defaults),
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.cache_type = REGCACHE_FLAT,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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};
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EXPORT_SYMBOL_GPL(mcp23x17_regmap);
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static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val)
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{
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return regmap_read(mcp->regmap, reg << mcp->reg_shift, val);
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}
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static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val)
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{
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return regmap_write(mcp->regmap, reg << mcp->reg_shift, val);
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}
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static int mcp_set_mask(struct mcp23s08 *mcp, unsigned int reg,
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unsigned int mask, bool enabled)
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{
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u16 val = enabled ? 0xffff : 0x0000;
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return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift,
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mask, val);
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}
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static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg,
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unsigned int pin, bool enabled)
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{
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u16 mask = BIT(pin);
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return mcp_set_mask(mcp, reg, mask, enabled);
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}
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static const struct pinctrl_pin_desc mcp23x08_pins[] = {
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PINCTRL_PIN(0, "gpio0"),
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PINCTRL_PIN(1, "gpio1"),
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PINCTRL_PIN(2, "gpio2"),
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PINCTRL_PIN(3, "gpio3"),
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PINCTRL_PIN(4, "gpio4"),
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PINCTRL_PIN(5, "gpio5"),
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PINCTRL_PIN(6, "gpio6"),
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PINCTRL_PIN(7, "gpio7"),
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};
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static const struct pinctrl_pin_desc mcp23x17_pins[] = {
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PINCTRL_PIN(0, "gpio0"),
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PINCTRL_PIN(1, "gpio1"),
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PINCTRL_PIN(2, "gpio2"),
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PINCTRL_PIN(3, "gpio3"),
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PINCTRL_PIN(4, "gpio4"),
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PINCTRL_PIN(5, "gpio5"),
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PINCTRL_PIN(6, "gpio6"),
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PINCTRL_PIN(7, "gpio7"),
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PINCTRL_PIN(8, "gpio8"),
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PINCTRL_PIN(9, "gpio9"),
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PINCTRL_PIN(10, "gpio10"),
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PINCTRL_PIN(11, "gpio11"),
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PINCTRL_PIN(12, "gpio12"),
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PINCTRL_PIN(13, "gpio13"),
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PINCTRL_PIN(14, "gpio14"),
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PINCTRL_PIN(15, "gpio15"),
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};
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static int mcp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
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{
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return 0;
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}
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static const char *mcp_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
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unsigned int group)
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{
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return NULL;
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}
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static int mcp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
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unsigned int group,
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const unsigned int **pins,
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unsigned int *num_pins)
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{
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return -ENOTSUPP;
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}
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static const struct pinctrl_ops mcp_pinctrl_ops = {
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.get_groups_count = mcp_pinctrl_get_groups_count,
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.get_group_name = mcp_pinctrl_get_group_name,
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.get_group_pins = mcp_pinctrl_get_group_pins,
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#ifdef CONFIG_OF
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.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
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.dt_free_map = pinconf_generic_dt_free_map,
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#endif
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};
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static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
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unsigned long *config)
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{
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struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
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enum pin_config_param param = pinconf_to_config_param(*config);
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unsigned int data, status;
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int ret;
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switch (param) {
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case PIN_CONFIG_BIAS_PULL_UP:
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ret = mcp_read(mcp, MCP_GPPU, &data);
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if (ret < 0)
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return ret;
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status = (data & BIT(pin)) ? 1 : 0;
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break;
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default:
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return -ENOTSUPP;
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}
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*config = 0;
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return status ? 0 : -EINVAL;
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}
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static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
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unsigned long *configs, unsigned int num_configs)
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{
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struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
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enum pin_config_param param;
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u32 arg;
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int ret = 0;
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int i;
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for (i = 0; i < num_configs; i++) {
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param = pinconf_to_config_param(configs[i]);
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arg = pinconf_to_config_argument(configs[i]);
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switch (param) {
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case PIN_CONFIG_BIAS_PULL_UP:
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ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg);
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break;
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default:
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dev_dbg(mcp->dev, "Invalid config param %04x\n", param);
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return -ENOTSUPP;
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}
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}
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return ret;
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}
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static const struct pinconf_ops mcp_pinconf_ops = {
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.pin_config_get = mcp_pinconf_get,
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.pin_config_set = mcp_pinconf_set,
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.is_generic = true,
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};
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/*----------------------------------------------------------------------*/
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static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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struct mcp23s08 *mcp = gpiochip_get_data(chip);
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int status;
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mutex_lock(&mcp->lock);
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status = mcp_set_bit(mcp, MCP_IODIR, offset, true);
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mutex_unlock(&mcp->lock);
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return status;
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}
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static int mcp23s08_get(struct gpio_chip *chip, unsigned offset)
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{
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struct mcp23s08 *mcp = gpiochip_get_data(chip);
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int status, ret;
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mutex_lock(&mcp->lock);
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/* REVISIT reading this clears any IRQ ... */
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ret = mcp_read(mcp, MCP_GPIO, &status);
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if (ret < 0)
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status = 0;
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else {
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mcp->cached_gpio = status;
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status = !!(status & (1 << offset));
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}
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mutex_unlock(&mcp->lock);
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return status;
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}
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static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value)
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{
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return mcp_set_mask(mcp, MCP_OLAT, mask, value);
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}
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static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct mcp23s08 *mcp = gpiochip_get_data(chip);
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unsigned mask = BIT(offset);
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mutex_lock(&mcp->lock);
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__mcp23s08_set(mcp, mask, !!value);
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mutex_unlock(&mcp->lock);
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}
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static int
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mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct mcp23s08 *mcp = gpiochip_get_data(chip);
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unsigned mask = BIT(offset);
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int status;
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mutex_lock(&mcp->lock);
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status = __mcp23s08_set(mcp, mask, value);
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if (status == 0) {
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status = mcp_set_mask(mcp, MCP_IODIR, mask, false);
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}
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mutex_unlock(&mcp->lock);
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return status;
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}
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/*----------------------------------------------------------------------*/
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static irqreturn_t mcp23s08_irq(int irq, void *data)
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{
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struct mcp23s08 *mcp = data;
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int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval;
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unsigned int child_irq;
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bool intf_set, intcap_changed, gpio_bit_changed,
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defval_changed, gpio_set;
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mutex_lock(&mcp->lock);
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if (mcp_read(mcp, MCP_INTF, &intf))
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goto unlock;
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if (mcp_read(mcp, MCP_INTCAP, &intcap))
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goto unlock;
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if (mcp_read(mcp, MCP_INTCON, &intcon))
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goto unlock;
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if (mcp_read(mcp, MCP_DEFVAL, &defval))
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goto unlock;
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/* This clears the interrupt(configurable on S18) */
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if (mcp_read(mcp, MCP_GPIO, &gpio))
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goto unlock;
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gpio_orig = mcp->cached_gpio;
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mcp->cached_gpio = gpio;
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mutex_unlock(&mcp->lock);
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if (intf == 0) {
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/* There is no interrupt pending */
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return IRQ_HANDLED;
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}
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dev_dbg(mcp->chip.parent,
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"intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n",
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intcap, intf, gpio_orig, gpio);
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for (i = 0; i < mcp->chip.ngpio; i++) {
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/* We must check all of the inputs on the chip,
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* otherwise we may not notice a change on >=2 pins.
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*
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* On at least the mcp23s17, INTCAP is only updated
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* one byte at a time(INTCAPA and INTCAPB are
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* not written to at the same time - only on a per-bank
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* basis).
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*
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* INTF only contains the single bit that caused the
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* interrupt per-bank. On the mcp23s17, there is
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* INTFA and INTFB. If two pins are changed on the A
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* side at the same time, INTF will only have one bit
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* set. If one pin on the A side and one pin on the B
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* side are changed at the same time, INTF will have
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* two bits set. Thus, INTF can't be the only check
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* to see if the input has changed.
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*/
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intf_set = intf & BIT(i);
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if (i < 8 && intf_set)
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intcap_mask = 0x00FF;
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else if (i >= 8 && intf_set)
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intcap_mask = 0xFF00;
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else
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intcap_mask = 0x00;
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intcap_changed = (intcap_mask &
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(intcap & BIT(i))) !=
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(intcap_mask & (BIT(i) & gpio_orig));
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gpio_set = BIT(i) & gpio;
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gpio_bit_changed = (BIT(i) & gpio_orig) !=
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(BIT(i) & gpio);
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defval_changed = (BIT(i) & intcon) &&
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((BIT(i) & gpio) !=
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(BIT(i) & defval));
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if (((gpio_bit_changed || intcap_changed) &&
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(BIT(i) & mcp->irq_rise) && gpio_set) ||
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((gpio_bit_changed || intcap_changed) &&
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(BIT(i) & mcp->irq_fall) && !gpio_set) ||
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defval_changed) {
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child_irq = irq_find_mapping(mcp->chip.irq.domain, i);
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handle_nested_irq(child_irq);
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}
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}
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return IRQ_HANDLED;
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unlock:
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mutex_unlock(&mcp->lock);
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return IRQ_HANDLED;
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}
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static void mcp23s08_irq_mask(struct irq_data *data)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
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struct mcp23s08 *mcp = gpiochip_get_data(gc);
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unsigned int pos = data->hwirq;
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mcp_set_bit(mcp, MCP_GPINTEN, pos, false);
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}
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static void mcp23s08_irq_unmask(struct irq_data *data)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
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struct mcp23s08 *mcp = gpiochip_get_data(gc);
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unsigned int pos = data->hwirq;
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mcp_set_bit(mcp, MCP_GPINTEN, pos, true);
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}
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static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
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struct mcp23s08 *mcp = gpiochip_get_data(gc);
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unsigned int pos = data->hwirq;
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if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
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mcp_set_bit(mcp, MCP_INTCON, pos, false);
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mcp->irq_rise |= BIT(pos);
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mcp->irq_fall |= BIT(pos);
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} else if (type & IRQ_TYPE_EDGE_RISING) {
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mcp_set_bit(mcp, MCP_INTCON, pos, false);
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mcp->irq_rise |= BIT(pos);
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mcp->irq_fall &= ~BIT(pos);
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|
} else if (type & IRQ_TYPE_EDGE_FALLING) {
|
|
mcp_set_bit(mcp, MCP_INTCON, pos, false);
|
|
mcp->irq_rise &= ~BIT(pos);
|
|
mcp->irq_fall |= BIT(pos);
|
|
} else if (type & IRQ_TYPE_LEVEL_HIGH) {
|
|
mcp_set_bit(mcp, MCP_INTCON, pos, true);
|
|
mcp_set_bit(mcp, MCP_DEFVAL, pos, false);
|
|
} else if (type & IRQ_TYPE_LEVEL_LOW) {
|
|
mcp_set_bit(mcp, MCP_INTCON, pos, true);
|
|
mcp_set_bit(mcp, MCP_DEFVAL, pos, true);
|
|
} else
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void mcp23s08_irq_bus_lock(struct irq_data *data)
|
|
{
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
|
|
struct mcp23s08 *mcp = gpiochip_get_data(gc);
|
|
|
|
mutex_lock(&mcp->lock);
|
|
regcache_cache_only(mcp->regmap, true);
|
|
}
|
|
|
|
static void mcp23s08_irq_bus_unlock(struct irq_data *data)
|
|
{
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
|
|
struct mcp23s08 *mcp = gpiochip_get_data(gc);
|
|
|
|
regcache_cache_only(mcp->regmap, false);
|
|
regcache_sync(mcp->regmap);
|
|
|
|
mutex_unlock(&mcp->lock);
|
|
}
|
|
|
|
static int mcp23s08_irq_setup(struct mcp23s08 *mcp)
|
|
{
|
|
struct gpio_chip *chip = &mcp->chip;
|
|
int err;
|
|
unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED;
|
|
|
|
if (mcp->irq_active_high)
|
|
irqflags |= IRQF_TRIGGER_HIGH;
|
|
else
|
|
irqflags |= IRQF_TRIGGER_LOW;
|
|
|
|
err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL,
|
|
mcp23s08_irq,
|
|
irqflags, dev_name(chip->parent), mcp);
|
|
if (err != 0) {
|
|
dev_err(chip->parent, "unable to request IRQ#%d: %d\n",
|
|
mcp->irq, err);
|
|
return err;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*----------------------------------------------------------------------*/
|
|
|
|
int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
|
|
unsigned int addr, unsigned int type, unsigned int base)
|
|
{
|
|
int status, ret;
|
|
bool mirror = false;
|
|
bool open_drain = false;
|
|
|
|
mutex_init(&mcp->lock);
|
|
|
|
mcp->dev = dev;
|
|
mcp->addr = addr;
|
|
|
|
mcp->irq_active_high = false;
|
|
mcp->irq_chip.name = dev_name(dev);
|
|
mcp->irq_chip.irq_mask = mcp23s08_irq_mask;
|
|
mcp->irq_chip.irq_unmask = mcp23s08_irq_unmask;
|
|
mcp->irq_chip.irq_set_type = mcp23s08_irq_set_type;
|
|
mcp->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock;
|
|
mcp->irq_chip.irq_bus_sync_unlock = mcp23s08_irq_bus_unlock;
|
|
|
|
mcp->chip.direction_input = mcp23s08_direction_input;
|
|
mcp->chip.get = mcp23s08_get;
|
|
mcp->chip.direction_output = mcp23s08_direction_output;
|
|
mcp->chip.set = mcp23s08_set;
|
|
#ifdef CONFIG_OF_GPIO
|
|
mcp->chip.of_gpio_n_cells = 2;
|
|
mcp->chip.of_node = dev->of_node;
|
|
#endif
|
|
|
|
mcp->chip.base = base;
|
|
mcp->chip.can_sleep = true;
|
|
mcp->chip.parent = dev;
|
|
mcp->chip.owner = THIS_MODULE;
|
|
|
|
/* verify MCP_IOCON.SEQOP = 0, so sequential reads work,
|
|
* and MCP_IOCON.HAEN = 1, so we work with all chips.
|
|
*/
|
|
|
|
ret = mcp_read(mcp, MCP_IOCON, &status);
|
|
if (ret < 0)
|
|
return dev_err_probe(dev, ret, "can't identify chip %d\n", addr);
|
|
|
|
mcp->irq_controller =
|
|
device_property_read_bool(dev, "interrupt-controller");
|
|
if (mcp->irq && mcp->irq_controller) {
|
|
mcp->irq_active_high =
|
|
device_property_read_bool(dev,
|
|
"microchip,irq-active-high");
|
|
|
|
mirror = device_property_read_bool(dev, "microchip,irq-mirror");
|
|
open_drain = device_property_read_bool(dev, "drive-open-drain");
|
|
}
|
|
|
|
if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror ||
|
|
mcp->irq_active_high || open_drain) {
|
|
/* mcp23s17 has IOCON twice, make sure they are in sync */
|
|
status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8));
|
|
status |= IOCON_HAEN | (IOCON_HAEN << 8);
|
|
if (mcp->irq_active_high)
|
|
status |= IOCON_INTPOL | (IOCON_INTPOL << 8);
|
|
else
|
|
status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8));
|
|
|
|
if (mirror)
|
|
status |= IOCON_MIRROR | (IOCON_MIRROR << 8);
|
|
|
|
if (open_drain)
|
|
status |= IOCON_ODR | (IOCON_ODR << 8);
|
|
|
|
if (type == MCP_TYPE_S18 || type == MCP_TYPE_018)
|
|
status |= IOCON_INTCC | (IOCON_INTCC << 8);
|
|
|
|
ret = mcp_write(mcp, MCP_IOCON, status);
|
|
if (ret < 0)
|
|
return dev_err_probe(dev, ret, "can't write IOCON %d\n", addr);
|
|
}
|
|
|
|
if (mcp->irq && mcp->irq_controller) {
|
|
struct gpio_irq_chip *girq = &mcp->chip.irq;
|
|
|
|
girq->chip = &mcp->irq_chip;
|
|
/* This will let us handle the parent IRQ in the driver */
|
|
girq->parent_handler = NULL;
|
|
girq->num_parents = 0;
|
|
girq->parents = NULL;
|
|
girq->default_type = IRQ_TYPE_NONE;
|
|
girq->handler = handle_simple_irq;
|
|
girq->threaded = true;
|
|
}
|
|
|
|
ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);
|
|
if (ret < 0)
|
|
return dev_err_probe(dev, ret, "can't add GPIO chip\n");
|
|
|
|
mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops;
|
|
mcp->pinctrl_desc.confops = &mcp_pinconf_ops;
|
|
mcp->pinctrl_desc.npins = mcp->chip.ngpio;
|
|
if (mcp->pinctrl_desc.npins == 8)
|
|
mcp->pinctrl_desc.pins = mcp23x08_pins;
|
|
else if (mcp->pinctrl_desc.npins == 16)
|
|
mcp->pinctrl_desc.pins = mcp23x17_pins;
|
|
mcp->pinctrl_desc.owner = THIS_MODULE;
|
|
|
|
mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp);
|
|
if (IS_ERR(mcp->pctldev))
|
|
return dev_err_probe(dev, PTR_ERR(mcp->pctldev), "can't register controller\n");
|
|
|
|
if (mcp->irq) {
|
|
ret = mcp23s08_irq_setup(mcp);
|
|
if (ret)
|
|
return dev_err_probe(dev, ret, "can't setup IRQ\n");
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(mcp23s08_probe_one);
|
|
|
|
MODULE_LICENSE("GPL");
|