forked from Minki/linux
de725dec9d
Now that we rely on the number of handled overflows, ensure all handle_irq implementations actually return the right number. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Signed-off-by: Don Zickus <dzickus@redhat.com> Cc: peterz@infradead.org Cc: robert.richter@amd.com Cc: gorcunov@gmail.com Cc: fweisbec@gmail.com Cc: ying.huang@intel.com Cc: ming.m.lin@intel.com Cc: eranian@google.com LKML-Reference: <1283454469-1909-4-git-send-email-dzickus@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
1057 lines
28 KiB
C
1057 lines
28 KiB
C
#ifdef CONFIG_CPU_SUP_INTEL
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/*
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* Intel PerfMon, used on Core and later.
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*/
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static const u64 intel_perfmon_event_map[] =
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{
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[PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
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[PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
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[PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
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[PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
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[PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
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[PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
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};
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static struct event_constraint intel_core_event_constraints[] =
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{
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INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
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INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
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INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
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INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
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INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
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INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
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EVENT_CONSTRAINT_END
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};
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static struct event_constraint intel_core2_event_constraints[] =
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{
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FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
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/*
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* Core2 has Fixed Counter 2 listed as CPU_CLK_UNHALTED.REF and event
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* 0x013c as CPU_CLK_UNHALTED.BUS and specifies there is a fixed
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* ratio between these counters.
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*/
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/* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
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INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
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INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
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INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
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INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
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INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
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INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
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INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
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INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
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INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
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INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
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EVENT_CONSTRAINT_END
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};
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static struct event_constraint intel_nehalem_event_constraints[] =
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{
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FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
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/* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
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INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
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INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
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INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
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INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
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INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
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INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
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INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
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INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
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EVENT_CONSTRAINT_END
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};
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static struct event_constraint intel_westmere_event_constraints[] =
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{
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FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
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/* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
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INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
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INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
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INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
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INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
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EVENT_CONSTRAINT_END
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};
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static struct event_constraint intel_gen_event_constraints[] =
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{
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FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
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/* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
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EVENT_CONSTRAINT_END
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};
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static u64 intel_pmu_event_map(int hw_event)
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{
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return intel_perfmon_event_map[hw_event];
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}
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static __initconst const u64 westmere_hw_cache_event_ids
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] =
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{
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[ C(L1D) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
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[ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
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[ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
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[ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
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},
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},
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[ C(L1I ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
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[ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0x0,
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},
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},
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[ C(LL ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */
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[ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS */
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[ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */
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[ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */
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},
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},
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[ C(DTLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
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[ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
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[ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0x0,
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},
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},
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[ C(ITLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
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[ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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[ C(BPU ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
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[ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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};
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static __initconst const u64 nehalem_hw_cache_event_ids
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] =
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{
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[ C(L1D) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
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[ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
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[ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
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[ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
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},
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},
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[ C(L1I ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
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[ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0x0,
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},
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},
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[ C(LL ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */
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[ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS */
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[ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */
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[ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */
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},
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},
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[ C(DTLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
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[ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
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[ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0x0,
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},
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},
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[ C(ITLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
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[ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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[ C(BPU ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
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[ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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};
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static __initconst const u64 core2_hw_cache_event_ids
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] =
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{
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[ C(L1D) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
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[ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
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[ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
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[ C(RESULT_MISS) ] = 0,
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},
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},
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[ C(L1I ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
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[ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0,
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},
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},
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[ C(LL ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
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[ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
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[ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0,
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},
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},
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[ C(DTLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
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[ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
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[ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0,
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[ C(RESULT_MISS) ] = 0,
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},
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},
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[ C(ITLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
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[ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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[ C(BPU ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
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[ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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};
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static __initconst const u64 atom_hw_cache_event_ids
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] =
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{
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[ C(L1D) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
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[ C(RESULT_MISS) ] = 0,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
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[ C(RESULT_MISS) ] = 0,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0,
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},
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},
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[ C(L1I ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
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[ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
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},
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[ C(OP_WRITE) ] = {
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
[ C(RESULT_MISS) ] = -1,
|
|
},
|
|
[ C(OP_PREFETCH) ] = {
|
|
[ C(RESULT_ACCESS) ] = 0,
|
|
[ C(RESULT_MISS) ] = 0,
|
|
},
|
|
},
|
|
[ C(LL ) ] = {
|
|
[ C(OP_READ) ] = {
|
|
[ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
|
|
[ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
|
|
},
|
|
[ C(OP_WRITE) ] = {
|
|
[ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
|
|
[ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
|
|
},
|
|
[ C(OP_PREFETCH) ] = {
|
|
[ C(RESULT_ACCESS) ] = 0,
|
|
[ C(RESULT_MISS) ] = 0,
|
|
},
|
|
},
|
|
[ C(DTLB) ] = {
|
|
[ C(OP_READ) ] = {
|
|
[ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
|
|
[ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
|
|
},
|
|
[ C(OP_WRITE) ] = {
|
|
[ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
|
|
[ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
|
|
},
|
|
[ C(OP_PREFETCH) ] = {
|
|
[ C(RESULT_ACCESS) ] = 0,
|
|
[ C(RESULT_MISS) ] = 0,
|
|
},
|
|
},
|
|
[ C(ITLB) ] = {
|
|
[ C(OP_READ) ] = {
|
|
[ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
|
|
[ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
|
|
},
|
|
[ C(OP_WRITE) ] = {
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
[ C(RESULT_MISS) ] = -1,
|
|
},
|
|
[ C(OP_PREFETCH) ] = {
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
[ C(RESULT_MISS) ] = -1,
|
|
},
|
|
},
|
|
[ C(BPU ) ] = {
|
|
[ C(OP_READ) ] = {
|
|
[ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
|
|
[ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
|
|
},
|
|
[ C(OP_WRITE) ] = {
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
[ C(RESULT_MISS) ] = -1,
|
|
},
|
|
[ C(OP_PREFETCH) ] = {
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
[ C(RESULT_MISS) ] = -1,
|
|
},
|
|
},
|
|
};
|
|
|
|
static void intel_pmu_disable_all(void)
|
|
{
|
|
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
|
|
|
wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
|
|
|
|
if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
|
|
intel_pmu_disable_bts();
|
|
|
|
intel_pmu_pebs_disable_all();
|
|
intel_pmu_lbr_disable_all();
|
|
}
|
|
|
|
static void intel_pmu_enable_all(int added)
|
|
{
|
|
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
|
|
|
intel_pmu_pebs_enable_all();
|
|
intel_pmu_lbr_enable_all();
|
|
wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
|
|
|
|
if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
|
|
struct perf_event *event =
|
|
cpuc->events[X86_PMC_IDX_FIXED_BTS];
|
|
|
|
if (WARN_ON_ONCE(!event))
|
|
return;
|
|
|
|
intel_pmu_enable_bts(event->hw.config);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Workaround for:
|
|
* Intel Errata AAK100 (model 26)
|
|
* Intel Errata AAP53 (model 30)
|
|
* Intel Errata BD53 (model 44)
|
|
*
|
|
* The official story:
|
|
* These chips need to be 'reset' when adding counters by programming the
|
|
* magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
|
|
* in sequence on the same PMC or on different PMCs.
|
|
*
|
|
* In practise it appears some of these events do in fact count, and
|
|
* we need to programm all 4 events.
|
|
*/
|
|
static void intel_pmu_nhm_workaround(void)
|
|
{
|
|
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
|
static const unsigned long nhm_magic[4] = {
|
|
0x4300B5,
|
|
0x4300D2,
|
|
0x4300B1,
|
|
0x4300B1
|
|
};
|
|
struct perf_event *event;
|
|
int i;
|
|
|
|
/*
|
|
* The Errata requires below steps:
|
|
* 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
|
|
* 2) Configure 4 PERFEVTSELx with the magic events and clear
|
|
* the corresponding PMCx;
|
|
* 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
|
|
* 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
|
|
* 5) Clear 4 pairs of ERFEVTSELx and PMCx;
|
|
*/
|
|
|
|
/*
|
|
* The real steps we choose are a little different from above.
|
|
* A) To reduce MSR operations, we don't run step 1) as they
|
|
* are already cleared before this function is called;
|
|
* B) Call x86_perf_event_update to save PMCx before configuring
|
|
* PERFEVTSELx with magic number;
|
|
* C) With step 5), we do clear only when the PERFEVTSELx is
|
|
* not used currently.
|
|
* D) Call x86_perf_event_set_period to restore PMCx;
|
|
*/
|
|
|
|
/* We always operate 4 pairs of PERF Counters */
|
|
for (i = 0; i < 4; i++) {
|
|
event = cpuc->events[i];
|
|
if (event)
|
|
x86_perf_event_update(event);
|
|
}
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
|
|
wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
|
|
}
|
|
|
|
wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
|
|
wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
event = cpuc->events[i];
|
|
|
|
if (event) {
|
|
x86_perf_event_set_period(event);
|
|
__x86_pmu_enable_event(&event->hw,
|
|
ARCH_PERFMON_EVENTSEL_ENABLE);
|
|
} else
|
|
wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
|
|
}
|
|
}
|
|
|
|
static void intel_pmu_nhm_enable_all(int added)
|
|
{
|
|
if (added)
|
|
intel_pmu_nhm_workaround();
|
|
intel_pmu_enable_all(added);
|
|
}
|
|
|
|
static inline u64 intel_pmu_get_status(void)
|
|
{
|
|
u64 status;
|
|
|
|
rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
|
|
|
|
return status;
|
|
}
|
|
|
|
static inline void intel_pmu_ack_status(u64 ack)
|
|
{
|
|
wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
|
|
}
|
|
|
|
static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
|
|
{
|
|
int idx = hwc->idx - X86_PMC_IDX_FIXED;
|
|
u64 ctrl_val, mask;
|
|
|
|
mask = 0xfULL << (idx * 4);
|
|
|
|
rdmsrl(hwc->config_base, ctrl_val);
|
|
ctrl_val &= ~mask;
|
|
wrmsrl(hwc->config_base, ctrl_val);
|
|
}
|
|
|
|
static void intel_pmu_disable_event(struct perf_event *event)
|
|
{
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
|
|
if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
|
|
intel_pmu_disable_bts();
|
|
intel_pmu_drain_bts_buffer();
|
|
return;
|
|
}
|
|
|
|
if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
|
|
intel_pmu_disable_fixed(hwc);
|
|
return;
|
|
}
|
|
|
|
x86_pmu_disable_event(event);
|
|
|
|
if (unlikely(event->attr.precise_ip))
|
|
intel_pmu_pebs_disable(event);
|
|
}
|
|
|
|
static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
|
|
{
|
|
int idx = hwc->idx - X86_PMC_IDX_FIXED;
|
|
u64 ctrl_val, bits, mask;
|
|
|
|
/*
|
|
* Enable IRQ generation (0x8),
|
|
* and enable ring-3 counting (0x2) and ring-0 counting (0x1)
|
|
* if requested:
|
|
*/
|
|
bits = 0x8ULL;
|
|
if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
|
|
bits |= 0x2;
|
|
if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
|
|
bits |= 0x1;
|
|
|
|
/*
|
|
* ANY bit is supported in v3 and up
|
|
*/
|
|
if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
|
|
bits |= 0x4;
|
|
|
|
bits <<= (idx * 4);
|
|
mask = 0xfULL << (idx * 4);
|
|
|
|
rdmsrl(hwc->config_base, ctrl_val);
|
|
ctrl_val &= ~mask;
|
|
ctrl_val |= bits;
|
|
wrmsrl(hwc->config_base, ctrl_val);
|
|
}
|
|
|
|
static void intel_pmu_enable_event(struct perf_event *event)
|
|
{
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
|
|
if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
|
|
if (!__get_cpu_var(cpu_hw_events).enabled)
|
|
return;
|
|
|
|
intel_pmu_enable_bts(hwc->config);
|
|
return;
|
|
}
|
|
|
|
if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
|
|
intel_pmu_enable_fixed(hwc);
|
|
return;
|
|
}
|
|
|
|
if (unlikely(event->attr.precise_ip))
|
|
intel_pmu_pebs_enable(event);
|
|
|
|
__x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
|
|
}
|
|
|
|
/*
|
|
* Save and restart an expired event. Called by NMI contexts,
|
|
* so it has to be careful about preempting normal event ops:
|
|
*/
|
|
static int intel_pmu_save_and_restart(struct perf_event *event)
|
|
{
|
|
x86_perf_event_update(event);
|
|
return x86_perf_event_set_period(event);
|
|
}
|
|
|
|
static void intel_pmu_reset(void)
|
|
{
|
|
struct debug_store *ds = __get_cpu_var(cpu_hw_events).ds;
|
|
unsigned long flags;
|
|
int idx;
|
|
|
|
if (!x86_pmu.num_counters)
|
|
return;
|
|
|
|
local_irq_save(flags);
|
|
|
|
printk("clearing PMU state on CPU#%d\n", smp_processor_id());
|
|
|
|
for (idx = 0; idx < x86_pmu.num_counters; idx++) {
|
|
checking_wrmsrl(x86_pmu.eventsel + idx, 0ull);
|
|
checking_wrmsrl(x86_pmu.perfctr + idx, 0ull);
|
|
}
|
|
for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
|
|
checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
|
|
|
|
if (ds)
|
|
ds->bts_index = ds->bts_buffer_base;
|
|
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
/*
|
|
* This handler is triggered by the local APIC, so the APIC IRQ handling
|
|
* rules apply:
|
|
*/
|
|
static int intel_pmu_handle_irq(struct pt_regs *regs)
|
|
{
|
|
struct perf_sample_data data;
|
|
struct cpu_hw_events *cpuc;
|
|
int bit, loops;
|
|
u64 status;
|
|
int handled = 0;
|
|
|
|
perf_sample_data_init(&data, 0);
|
|
|
|
cpuc = &__get_cpu_var(cpu_hw_events);
|
|
|
|
intel_pmu_disable_all();
|
|
intel_pmu_drain_bts_buffer();
|
|
status = intel_pmu_get_status();
|
|
if (!status) {
|
|
intel_pmu_enable_all(0);
|
|
return 0;
|
|
}
|
|
|
|
loops = 0;
|
|
again:
|
|
intel_pmu_ack_status(status);
|
|
if (++loops > 100) {
|
|
WARN_ONCE(1, "perfevents: irq loop stuck!\n");
|
|
perf_event_print_debug();
|
|
intel_pmu_reset();
|
|
goto done;
|
|
}
|
|
|
|
inc_irq_stat(apic_perf_irqs);
|
|
|
|
intel_pmu_lbr_read();
|
|
|
|
/*
|
|
* PEBS overflow sets bit 62 in the global status register
|
|
*/
|
|
if (__test_and_clear_bit(62, (unsigned long *)&status)) {
|
|
handled++;
|
|
x86_pmu.drain_pebs(regs);
|
|
}
|
|
|
|
for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
|
|
struct perf_event *event = cpuc->events[bit];
|
|
|
|
handled++;
|
|
|
|
if (!test_bit(bit, cpuc->active_mask))
|
|
continue;
|
|
|
|
if (!intel_pmu_save_and_restart(event))
|
|
continue;
|
|
|
|
data.period = event->hw.last_period;
|
|
|
|
if (perf_event_overflow(event, 1, &data, regs))
|
|
x86_pmu_stop(event);
|
|
}
|
|
|
|
/*
|
|
* Repeat if there is more work to be done:
|
|
*/
|
|
status = intel_pmu_get_status();
|
|
if (status)
|
|
goto again;
|
|
|
|
done:
|
|
intel_pmu_enable_all(0);
|
|
return handled;
|
|
}
|
|
|
|
static struct event_constraint *
|
|
intel_bts_constraints(struct perf_event *event)
|
|
{
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
unsigned int hw_event, bts_event;
|
|
|
|
hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
|
|
bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
|
|
|
|
if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
|
|
return &bts_constraint;
|
|
|
|
return NULL;
|
|
}
|
|
|
|
static struct event_constraint *
|
|
intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
|
|
{
|
|
struct event_constraint *c;
|
|
|
|
c = intel_bts_constraints(event);
|
|
if (c)
|
|
return c;
|
|
|
|
c = intel_pebs_constraints(event);
|
|
if (c)
|
|
return c;
|
|
|
|
return x86_get_event_constraints(cpuc, event);
|
|
}
|
|
|
|
static int intel_pmu_hw_config(struct perf_event *event)
|
|
{
|
|
int ret = x86_pmu_hw_config(event);
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (event->attr.type != PERF_TYPE_RAW)
|
|
return 0;
|
|
|
|
if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
|
|
return 0;
|
|
|
|
if (x86_pmu.version < 3)
|
|
return -EINVAL;
|
|
|
|
if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
|
|
return -EACCES;
|
|
|
|
event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static __initconst const struct x86_pmu core_pmu = {
|
|
.name = "core",
|
|
.handle_irq = x86_pmu_handle_irq,
|
|
.disable_all = x86_pmu_disable_all,
|
|
.enable_all = x86_pmu_enable_all,
|
|
.enable = x86_pmu_enable_event,
|
|
.disable = x86_pmu_disable_event,
|
|
.hw_config = x86_pmu_hw_config,
|
|
.schedule_events = x86_schedule_events,
|
|
.eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
|
|
.perfctr = MSR_ARCH_PERFMON_PERFCTR0,
|
|
.event_map = intel_pmu_event_map,
|
|
.max_events = ARRAY_SIZE(intel_perfmon_event_map),
|
|
.apic = 1,
|
|
/*
|
|
* Intel PMCs cannot be accessed sanely above 32 bit width,
|
|
* so we install an artificial 1<<31 period regardless of
|
|
* the generic event period:
|
|
*/
|
|
.max_period = (1ULL << 31) - 1,
|
|
.get_event_constraints = intel_get_event_constraints,
|
|
.event_constraints = intel_core_event_constraints,
|
|
};
|
|
|
|
static void intel_pmu_cpu_starting(int cpu)
|
|
{
|
|
init_debug_store_on_cpu(cpu);
|
|
/*
|
|
* Deal with CPUs that don't clear their LBRs on power-up.
|
|
*/
|
|
intel_pmu_lbr_reset();
|
|
}
|
|
|
|
static void intel_pmu_cpu_dying(int cpu)
|
|
{
|
|
fini_debug_store_on_cpu(cpu);
|
|
}
|
|
|
|
static __initconst const struct x86_pmu intel_pmu = {
|
|
.name = "Intel",
|
|
.handle_irq = intel_pmu_handle_irq,
|
|
.disable_all = intel_pmu_disable_all,
|
|
.enable_all = intel_pmu_enable_all,
|
|
.enable = intel_pmu_enable_event,
|
|
.disable = intel_pmu_disable_event,
|
|
.hw_config = intel_pmu_hw_config,
|
|
.schedule_events = x86_schedule_events,
|
|
.eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
|
|
.perfctr = MSR_ARCH_PERFMON_PERFCTR0,
|
|
.event_map = intel_pmu_event_map,
|
|
.max_events = ARRAY_SIZE(intel_perfmon_event_map),
|
|
.apic = 1,
|
|
/*
|
|
* Intel PMCs cannot be accessed sanely above 32 bit width,
|
|
* so we install an artificial 1<<31 period regardless of
|
|
* the generic event period:
|
|
*/
|
|
.max_period = (1ULL << 31) - 1,
|
|
.get_event_constraints = intel_get_event_constraints,
|
|
|
|
.cpu_starting = intel_pmu_cpu_starting,
|
|
.cpu_dying = intel_pmu_cpu_dying,
|
|
};
|
|
|
|
static void intel_clovertown_quirks(void)
|
|
{
|
|
/*
|
|
* PEBS is unreliable due to:
|
|
*
|
|
* AJ67 - PEBS may experience CPL leaks
|
|
* AJ68 - PEBS PMI may be delayed by one event
|
|
* AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
|
|
* AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
|
|
*
|
|
* AJ67 could be worked around by restricting the OS/USR flags.
|
|
* AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
|
|
*
|
|
* AJ106 could possibly be worked around by not allowing LBR
|
|
* usage from PEBS, including the fixup.
|
|
* AJ68 could possibly be worked around by always programming
|
|
* a pebs_event_reset[0] value and coping with the lost events.
|
|
*
|
|
* But taken together it might just make sense to not enable PEBS on
|
|
* these chips.
|
|
*/
|
|
printk(KERN_WARNING "PEBS disabled due to CPU errata.\n");
|
|
x86_pmu.pebs = 0;
|
|
x86_pmu.pebs_constraints = NULL;
|
|
}
|
|
|
|
static __init int intel_pmu_init(void)
|
|
{
|
|
union cpuid10_edx edx;
|
|
union cpuid10_eax eax;
|
|
unsigned int unused;
|
|
unsigned int ebx;
|
|
int version;
|
|
|
|
if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
|
|
switch (boot_cpu_data.x86) {
|
|
case 0x6:
|
|
return p6_pmu_init();
|
|
case 0xf:
|
|
return p4_pmu_init();
|
|
}
|
|
return -ENODEV;
|
|
}
|
|
|
|
/*
|
|
* Check whether the Architectural PerfMon supports
|
|
* Branch Misses Retired hw_event or not.
|
|
*/
|
|
cpuid(10, &eax.full, &ebx, &unused, &edx.full);
|
|
if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
|
|
return -ENODEV;
|
|
|
|
version = eax.split.version_id;
|
|
if (version < 2)
|
|
x86_pmu = core_pmu;
|
|
else
|
|
x86_pmu = intel_pmu;
|
|
|
|
x86_pmu.version = version;
|
|
x86_pmu.num_counters = eax.split.num_counters;
|
|
x86_pmu.cntval_bits = eax.split.bit_width;
|
|
x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
|
|
|
|
/*
|
|
* Quirk: v2 perfmon does not report fixed-purpose events, so
|
|
* assume at least 3 events:
|
|
*/
|
|
if (version > 1)
|
|
x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
|
|
|
|
/*
|
|
* v2 and above have a perf capabilities MSR
|
|
*/
|
|
if (version > 1) {
|
|
u64 capabilities;
|
|
|
|
rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
|
|
x86_pmu.intel_cap.capabilities = capabilities;
|
|
}
|
|
|
|
intel_ds_init();
|
|
|
|
/*
|
|
* Install the hw-cache-events table:
|
|
*/
|
|
switch (boot_cpu_data.x86_model) {
|
|
case 14: /* 65 nm core solo/duo, "Yonah" */
|
|
pr_cont("Core events, ");
|
|
break;
|
|
|
|
case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
|
|
x86_pmu.quirks = intel_clovertown_quirks;
|
|
case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
|
|
case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
|
|
case 29: /* six-core 45 nm xeon "Dunnington" */
|
|
memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
|
|
sizeof(hw_cache_event_ids));
|
|
|
|
intel_pmu_lbr_init_core();
|
|
|
|
x86_pmu.event_constraints = intel_core2_event_constraints;
|
|
pr_cont("Core2 events, ");
|
|
break;
|
|
|
|
case 26: /* 45 nm nehalem, "Bloomfield" */
|
|
case 30: /* 45 nm nehalem, "Lynnfield" */
|
|
case 46: /* 45 nm nehalem-ex, "Beckton" */
|
|
memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
|
|
sizeof(hw_cache_event_ids));
|
|
|
|
intel_pmu_lbr_init_nhm();
|
|
|
|
x86_pmu.event_constraints = intel_nehalem_event_constraints;
|
|
x86_pmu.enable_all = intel_pmu_nhm_enable_all;
|
|
pr_cont("Nehalem events, ");
|
|
break;
|
|
|
|
case 28: /* Atom */
|
|
memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
|
|
sizeof(hw_cache_event_ids));
|
|
|
|
intel_pmu_lbr_init_atom();
|
|
|
|
x86_pmu.event_constraints = intel_gen_event_constraints;
|
|
pr_cont("Atom events, ");
|
|
break;
|
|
|
|
case 37: /* 32 nm nehalem, "Clarkdale" */
|
|
case 44: /* 32 nm nehalem, "Gulftown" */
|
|
memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
|
|
sizeof(hw_cache_event_ids));
|
|
|
|
intel_pmu_lbr_init_nhm();
|
|
|
|
x86_pmu.event_constraints = intel_westmere_event_constraints;
|
|
x86_pmu.enable_all = intel_pmu_nhm_enable_all;
|
|
pr_cont("Westmere events, ");
|
|
break;
|
|
|
|
default:
|
|
/*
|
|
* default constraints for v2 and up
|
|
*/
|
|
x86_pmu.event_constraints = intel_gen_event_constraints;
|
|
pr_cont("generic architected perfmon, ");
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
#else /* CONFIG_CPU_SUP_INTEL */
|
|
|
|
static int intel_pmu_init(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
#endif /* CONFIG_CPU_SUP_INTEL */
|