forked from Minki/linux
b3901d54dc
The patch adds support for thread creation and context switching. The context switching CPU specific code is introduced with the CPU support patch (part of the arch/arm64/mm/proc.S file). AArch64 supports ASID-tagged TLBs and the ASID can be either 8 or 16-bit wide (detectable via the ID_AA64AFR0_EL1 register). Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de> |
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.. | ||
asm-offsets.h | ||
assembler.h | ||
memblock.h | ||
memory.h | ||
mmu_context.h | ||
mmu.h | ||
page.h | ||
pgalloc.h | ||
pgtable-2level-hwdef.h | ||
pgtable-2level-types.h | ||
pgtable-3level-hwdef.h | ||
pgtable-3level-types.h | ||
pgtable-hwdef.h | ||
pgtable.h | ||
ptrace.h | ||
setup.h | ||
sparsemem.h | ||
stacktrace.h | ||
thread_info.h | ||
traps.h |