forked from Minki/linux
b35e6d9a1c
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
455 lines
12 KiB
C
455 lines
12 KiB
C
/*
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Broadcom B43 wireless driver
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IEEE 802.11n LCN-PHY support
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING. If not, write to
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the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
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Boston, MA 02110-1301, USA.
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*/
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#include <linux/slab.h>
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#include "b43.h"
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#include "phy_lcn.h"
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#include "tables_phy_lcn.h"
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#include "main.h"
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/**************************************************
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* Radio 2064.
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**************************************************/
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static void b43_radio_2064_channel_setup(struct b43_wldev *dev)
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{
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u16 save[2];
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b43_radio_set(dev, 0x09d, 0x4);
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b43_radio_write(dev, 0x09e, 0xf);
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b43_radio_write(dev, 0x02a, 0xb);
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b43_radio_maskset(dev, 0x030, ~0x3, 0xa);
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b43_radio_maskset(dev, 0x091, ~0x3, 0);
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b43_radio_maskset(dev, 0x038, ~0xf, 0x7);
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b43_radio_maskset(dev, 0x030, ~0xc, 0x8);
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b43_radio_maskset(dev, 0x05e, ~0xf, 0x8);
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b43_radio_maskset(dev, 0x05e, ~0xf0, 0x80);
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b43_radio_write(dev, 0x06c, 0x80);
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save[0] = b43_radio_read(dev, 0x044);
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save[1] = b43_radio_read(dev, 0x12b);
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b43_radio_set(dev, 0x044, 0x7);
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b43_radio_set(dev, 0x12b, 0xe);
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/* TODO */
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b43_radio_write(dev, 0x040, 0xfb);
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b43_radio_write(dev, 0x041, 0x9a);
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b43_radio_write(dev, 0x042, 0xa3);
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b43_radio_write(dev, 0x043, 0x0c);
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/* TODO */
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b43_radio_set(dev, 0x044, 0x0c);
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udelay(1);
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b43_radio_write(dev, 0x044, save[0]);
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b43_radio_write(dev, 0x12b, save[1]);
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b43_radio_write(dev, 0x038, 0x0);
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b43_radio_write(dev, 0x091, 0x7);
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}
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static void b43_radio_2064_init(struct b43_wldev *dev)
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{
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b43_radio_write(dev, 0x09c, 0x0020);
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b43_radio_write(dev, 0x105, 0x0008);
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b43_radio_write(dev, 0x032, 0x0062);
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b43_radio_write(dev, 0x033, 0x0019);
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b43_radio_write(dev, 0x090, 0x0010);
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b43_radio_write(dev, 0x010, 0x0000);
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b43_radio_write(dev, 0x060, 0x007f);
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b43_radio_write(dev, 0x061, 0x0072);
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b43_radio_write(dev, 0x062, 0x007f);
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b43_radio_write(dev, 0x01d, 0x0002);
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b43_radio_write(dev, 0x01e, 0x0006);
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b43_phy_write(dev, 0x4ea, 0x4688);
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b43_phy_maskset(dev, 0x4eb, ~0x7, 0x2);
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b43_phy_mask(dev, 0x4eb, ~0x01c0);
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b43_phy_maskset(dev, 0x46a, 0xff00, 0x19);
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b43_lcntab_write(dev, B43_LCNTAB16(0x00, 0x55), 0);
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b43_radio_mask(dev, 0x05b, (u16) ~0xff02);
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b43_radio_set(dev, 0x004, 0x40);
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b43_radio_set(dev, 0x120, 0x10);
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b43_radio_set(dev, 0x078, 0x80);
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b43_radio_set(dev, 0x129, 0x2);
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b43_radio_set(dev, 0x057, 0x1);
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b43_radio_set(dev, 0x05b, 0x2);
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/* TODO: wait for some bit to be set */
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b43_radio_read(dev, 0x05c);
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b43_radio_mask(dev, 0x05b, (u16) ~0xff02);
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b43_radio_mask(dev, 0x057, (u16) ~0xff01);
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b43_phy_write(dev, 0x933, 0x2d6b);
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b43_phy_write(dev, 0x934, 0x2d6b);
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b43_phy_write(dev, 0x935, 0x2d6b);
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b43_phy_write(dev, 0x936, 0x2d6b);
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b43_phy_write(dev, 0x937, 0x016b);
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b43_radio_mask(dev, 0x057, (u16) ~0xff02);
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b43_radio_write(dev, 0x0c2, 0x006f);
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}
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/**************************************************
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* Various PHY ops
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**************************************************/
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static void b43_phy_lcn_afe_set_unset(struct b43_wldev *dev)
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{
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u16 afe_ctl2 = b43_phy_read(dev, B43_PHY_LCN_AFE_CTL2);
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u16 afe_ctl1 = b43_phy_read(dev, B43_PHY_LCN_AFE_CTL1);
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b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2 | 0x1);
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b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1 | 0x1);
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b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2 & ~0x1);
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b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1 & ~0x1);
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b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2);
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b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1);
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}
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static void b43_phy_lcn_clear_0x07_table(struct b43_wldev *dev)
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{
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u8 i;
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b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) | 0x340);
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for (i = 0; i < 30; i++) {
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b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, 0);
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b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, 0);
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}
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b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) | 0x80);
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for (i = 0; i < 64; i++) {
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b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, 0);
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b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, 0);
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}
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}
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static void b43_phy_lcn_pre_radio_init(struct b43_wldev *dev)
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{
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b43_radio_write(dev, 0x11c, 0);
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b43_phy_write(dev, 0x43b, 0);
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b43_phy_write(dev, 0x43c, 0);
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b43_phy_write(dev, 0x44c, 0);
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b43_phy_write(dev, 0x4e6, 0);
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b43_phy_write(dev, 0x4f9, 0);
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b43_phy_write(dev, 0x4b0, 0);
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b43_phy_write(dev, 0x938, 0);
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b43_phy_write(dev, 0x4b0, 0);
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b43_phy_write(dev, 0x44e, 0);
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b43_phy_set(dev, 0x567, 0x03);
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b43_phy_set(dev, 0x44a, 0x44);
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b43_phy_write(dev, 0x44a, 0x80);
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b43_phy_maskset(dev, 0x634, ~0xff, 0xc);
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b43_phy_maskset(dev, 0x634, ~0xff, 0xa);
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b43_phy_write(dev, 0x910, 0x1);
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b43_phy_maskset(dev, 0x448, ~0x300, 0x100);
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b43_phy_maskset(dev, 0x608, ~0xff, 0x17);
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b43_phy_maskset(dev, 0x604, ~0x7ff, 0x3ea);
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b43_phy_set(dev, 0x805, 0x1);
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b43_phy_maskset(dev, 0x42f, ~0x7, 0x3);
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b43_phy_maskset(dev, 0x030, ~0x7, 0x3);
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b43_phy_write(dev, 0x414, 0x1e10);
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b43_phy_write(dev, 0x415, 0x0640);
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b43_phy_maskset(dev, 0x4df, (u16) ~0xff00, 0xf700);
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b43_phy_set(dev, 0x44a, 0x44);
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b43_phy_write(dev, 0x44a, 0x80);
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b43_phy_maskset(dev, 0x434, ~0xff, 0xfd);
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b43_phy_maskset(dev, 0x420, ~0xff, 0x10);
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b43_radio_set(dev, 0x09b, 0xf0);
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b43_phy_write(dev, 0x7d6, 0x0902);
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/* TODO: more ops */
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}
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static void b43_phy_lcn_save_configsth_restore(struct b43_wldev *dev)
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{
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u8 i;
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u16 save_radio_regs[6][2] = {
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{ 0x007, 0 }, { 0x0ff, 0 }, { 0x11f, 0 }, { 0x005, 0 },
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{ 0x025, 0 }, { 0x112, 0 },
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};
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u16 save_phy_regs[14][2] = {
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{ 0x503, 0 }, { 0x4a4, 0 }, { 0x4d0, 0 }, { 0x4d9, 0 },
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{ 0x4da, 0 }, { 0x4a6, 0 }, { 0x938, 0 }, { 0x939, 0 },
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{ 0x4d8, 0 }, { 0x4d0, 0 }, { 0x4d7, 0 }, { 0x4a5, 0 },
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{ 0x40d, 0 }, { 0x4a2, 0 },
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};
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u16 save_radio_4a4;
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for (i = 0; i < 6; i++)
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save_radio_regs[i][1] = b43_radio_read(dev,
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save_radio_regs[i][0]);
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for (i = 0; i < 14; i++)
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save_phy_regs[i][1] = b43_phy_read(dev, save_phy_regs[i][0]);
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save_radio_4a4 = b43_radio_read(dev, 0x4a4);
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/* TODO: config sth */
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for (i = 0; i < 6; i++)
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b43_radio_write(dev, save_radio_regs[i][0],
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save_radio_regs[i][1]);
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for (i = 0; i < 14; i++)
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b43_phy_write(dev, save_phy_regs[i][0], save_phy_regs[i][1]);
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b43_radio_write(dev, 0x4a4, save_radio_4a4);
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}
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/**************************************************
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* Channel switching ops.
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**************************************************/
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static int b43_phy_lcn_set_channel(struct b43_wldev *dev,
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struct ieee80211_channel *channel,
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enum nl80211_channel_type channel_type)
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{
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/* TODO: PLL and PHY ops */
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b43_phy_set(dev, 0x44a, 0x44);
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b43_phy_write(dev, 0x44a, 0x80);
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b43_phy_set(dev, 0x44a, 0x44);
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b43_phy_write(dev, 0x44a, 0x80);
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b43_radio_2064_channel_setup(dev);
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mdelay(1);
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b43_phy_lcn_afe_set_unset(dev);
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/* TODO */
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return 0;
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}
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/**************************************************
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* Basic PHY ops.
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**************************************************/
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static int b43_phy_lcn_op_allocate(struct b43_wldev *dev)
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{
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struct b43_phy_lcn *phy_lcn;
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phy_lcn = kzalloc(sizeof(*phy_lcn), GFP_KERNEL);
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if (!phy_lcn)
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return -ENOMEM;
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dev->phy.lcn = phy_lcn;
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return 0;
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}
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static void b43_phy_lcn_op_free(struct b43_wldev *dev)
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{
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struct b43_phy *phy = &dev->phy;
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struct b43_phy_lcn *phy_lcn = phy->lcn;
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kfree(phy_lcn);
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phy->lcn = NULL;
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}
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static void b43_phy_lcn_op_prepare_structs(struct b43_wldev *dev)
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{
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struct b43_phy *phy = &dev->phy;
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struct b43_phy_lcn *phy_lcn = phy->lcn;
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memset(phy_lcn, 0, sizeof(*phy_lcn));
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}
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static int b43_phy_lcn_op_init(struct b43_wldev *dev)
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{
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b43_phy_set(dev, 0x44a, 0x80);
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b43_phy_mask(dev, 0x44a, 0x7f);
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b43_phy_set(dev, 0x6d1, 0x80);
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b43_phy_write(dev, 0x6d0, 0x7);
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b43_phy_lcn_afe_set_unset(dev);
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b43_phy_write(dev, 0x60a, 0xa0);
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b43_phy_write(dev, 0x46a, 0x19);
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b43_phy_maskset(dev, 0x663, 0xFF00, 0x64);
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b43_phy_lcn_tables_init(dev);
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b43_phy_lcn_pre_radio_init(dev);
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b43_phy_lcn_clear_0x07_table(dev);
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if (dev->phy.radio_ver == 0x2064)
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b43_radio_2064_init(dev);
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else
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B43_WARN_ON(1);
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b43_phy_lcn_save_configsth_restore(dev);
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return 0;
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}
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static void b43_phy_lcn_op_software_rfkill(struct b43_wldev *dev,
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bool blocked)
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{
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if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
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b43err(dev->wl, "MAC not suspended\n");
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if (blocked) {
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b43_phy_mask(dev, B43_PHY_LCN_RF_CTL2, ~0x7c00);
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b43_phy_set(dev, B43_PHY_LCN_RF_CTL1, 0x1f00);
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b43_phy_mask(dev, B43_PHY_LCN_RF_CTL5, ~0x7f00);
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b43_phy_mask(dev, B43_PHY_LCN_RF_CTL4, ~0x2);
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b43_phy_set(dev, B43_PHY_LCN_RF_CTL3, 0x808);
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b43_phy_mask(dev, B43_PHY_LCN_RF_CTL7, ~0x8);
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b43_phy_set(dev, B43_PHY_LCN_RF_CTL6, 0x8);
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} else {
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b43_phy_mask(dev, B43_PHY_LCN_RF_CTL1, ~0x1f00);
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b43_phy_mask(dev, B43_PHY_LCN_RF_CTL3, ~0x808);
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b43_phy_mask(dev, B43_PHY_LCN_RF_CTL6, ~0x8);
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}
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}
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static void b43_phy_lcn_op_switch_analog(struct b43_wldev *dev, bool on)
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{
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if (on) {
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b43_phy_mask(dev, B43_PHY_LCN_AFE_CTL1, ~0x7);
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} else {
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b43_phy_set(dev, B43_PHY_LCN_AFE_CTL2, 0x7);
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b43_phy_set(dev, B43_PHY_LCN_AFE_CTL1, 0x7);
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}
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}
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static int b43_phy_lcn_op_switch_channel(struct b43_wldev *dev,
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unsigned int new_channel)
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{
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struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
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enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
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if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
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if ((new_channel < 1) || (new_channel > 14))
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return -EINVAL;
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} else {
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return -EINVAL;
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}
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return b43_phy_lcn_set_channel(dev, channel, channel_type);
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}
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static unsigned int b43_phy_lcn_op_get_default_chan(struct b43_wldev *dev)
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{
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if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
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return 1;
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return 36;
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}
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static enum b43_txpwr_result
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b43_phy_lcn_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi)
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{
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return B43_TXPWR_RES_DONE;
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}
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static void b43_phy_lcn_op_adjust_txpower(struct b43_wldev *dev)
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{
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}
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/**************************************************
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* R/W ops.
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**************************************************/
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static u16 b43_phy_lcn_op_read(struct b43_wldev *dev, u16 reg)
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{
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b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
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return b43_read16(dev, B43_MMIO_PHY_DATA);
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}
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static void b43_phy_lcn_op_write(struct b43_wldev *dev, u16 reg, u16 value)
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{
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b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
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b43_write16(dev, B43_MMIO_PHY_DATA, value);
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}
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static void b43_phy_lcn_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
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u16 set)
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{
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b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
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b43_write16(dev, B43_MMIO_PHY_DATA,
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(b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
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}
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static u16 b43_phy_lcn_op_radio_read(struct b43_wldev *dev, u16 reg)
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{
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/* LCN-PHY needs 0x200 for read access */
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reg |= 0x200;
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b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
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return b43_read16(dev, B43_MMIO_RADIO24_DATA);
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}
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static void b43_phy_lcn_op_radio_write(struct b43_wldev *dev, u16 reg,
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u16 value)
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{
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b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
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b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
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}
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/**************************************************
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* PHY ops struct.
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**************************************************/
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const struct b43_phy_operations b43_phyops_lcn = {
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.allocate = b43_phy_lcn_op_allocate,
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.free = b43_phy_lcn_op_free,
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.prepare_structs = b43_phy_lcn_op_prepare_structs,
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.init = b43_phy_lcn_op_init,
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.phy_read = b43_phy_lcn_op_read,
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.phy_write = b43_phy_lcn_op_write,
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.phy_maskset = b43_phy_lcn_op_maskset,
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.radio_read = b43_phy_lcn_op_radio_read,
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.radio_write = b43_phy_lcn_op_radio_write,
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.software_rfkill = b43_phy_lcn_op_software_rfkill,
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.switch_analog = b43_phy_lcn_op_switch_analog,
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.switch_channel = b43_phy_lcn_op_switch_channel,
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.get_default_chan = b43_phy_lcn_op_get_default_chan,
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.recalc_txpower = b43_phy_lcn_op_recalc_txpower,
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.adjust_txpower = b43_phy_lcn_op_adjust_txpower,
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};
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