linux/arch/x86/events
Like Xu b2d6504761 perf/x86/lbr: Add interface to get LBR information
The LBR records msrs are model specific. The perf subsystem has already
obtained the base addresses of LBR records based on the cpu model.

Therefore, an interface is added to allow callers outside the perf
subsystem to obtain these LBR information. It's useful for hypervisors
to emulate the LBR feature for guests with less code.

Signed-off-by: Like Xu <like.xu@linux.intel.com>
Signed-off-by: Wei Wang <wei.w.wang@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200613080958.132489-4-like.xu@linux.intel.com
2020-07-02 15:51:46 +02:00
..
amd Merge branch 'x86/cpu' into perf/core, to resolve conflict 2020-03-25 15:20:44 +01:00
intel perf/x86/lbr: Add interface to get LBR information 2020-07-02 15:51:46 +02:00
zhaoxin x86/perf: Add hardware performance events support for Zhaoxin CPU. 2020-04-30 20:14:35 +02:00
core.c perf/x86/core: Refactor hw->idx checks and cleanup 2020-07-02 15:51:46 +02:00
Kconfig treewide: replace '---help---' in Kconfig files with 'help' 2020-06-14 01:57:21 +09:00
Makefile perf/x86/rapl: Fix RAPL config variable bug 2020-06-02 11:52:56 +02:00
msr.c perf/x86/msr: Add Tremont support 2020-02-11 13:17:50 +01:00
perf_event.h perf/x86: Fix variable types for LBR registers 2020-07-02 15:51:45 +02:00
probe.c perf/x86/rapl: Make perf_probe_msr() more robust and flexible 2020-05-28 07:58:55 +02:00
probe.h perf/x86: Add MSR probe interface 2019-06-24 19:28:31 +02:00
rapl.c perf/x86/rapl: Add AMD Fam17h RAPL support 2020-05-28 07:58:56 +02:00