forked from Minki/linux
b29de2de50
Due to a copy-paste error the uart1 and uart2 clock div set incorrect, fix it. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> |
||
---|---|---|
.. | ||
clk-cpu.c | ||
clk-inverter.c | ||
clk-mmc-phase.c | ||
clk-pll.c | ||
clk-rk3036.c | ||
clk-rk3188.c | ||
clk-rk3228.c | ||
clk-rk3288.c | ||
clk-rk3368.c | ||
clk-rockchip.c | ||
clk.c | ||
clk.h | ||
Makefile | ||
softrst.c |