forked from Minki/linux
485a40d7cd
Add devicetree bindings for Rockchip cru which found on Rockchip SoCs. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
63 lines
2.0 KiB
Plaintext
63 lines
2.0 KiB
Plaintext
* Rockchip RK3399 Clock and Reset Unit
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The RK3399 clock controller generates and supplies clock to various
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controllers within the SoC and also implements a reset controller for SoC
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peripherals.
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Required Properties:
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- compatible: PMU for CRU should be "rockchip,rk3399-pmucru"
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- compatible: CRU should be "rockchip,rk3399-cru"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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- #reset-cells: should be 1.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
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used in device tree sources. Similar macros exist for the reset sources in
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these files.
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External clocks:
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There are several clocks that are generated outside the SoC. It is expected
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that they are defined using standard clock bindings with following
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clock-output-names:
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- "xin24m" - crystal input - required,
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- "xin32k" - rtc clock - optional,
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- "clkin_gmac" - external GMAC clock - optional,
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- "clkin_i2s" - external I2S clock - optional,
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- "pclkin_cif" - external ISP clock - optional,
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- "clk_usbphy0_480m" - output clock of the pll in the usbphy0
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- "clk_usbphy1_480m" - output clock of the pll in the usbphy1
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Example: Clock controller node:
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pmucru: pmu-clock-controller@ff750000 {
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compatible = "rockchip,rk3399-pmucru";
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reg = <0x0 0xff750000 0x0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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cru: clock-controller@ff760000 {
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compatible = "rockchip,rk3399-cru";
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reg = <0x0 0xff760000 0x0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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Example: UART controller node that consumes the clock generated by the clock
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controller:
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uart0: serial@ff1a0000 {
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compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff180000 0x0 0x100>;
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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