forked from Minki/linux
b251e4c88f
The names of all fclk divider gate clocks follow the naming schema
"fclk_divN" and the name of all fclk fixed dividers follow the naming
schema "fclk_divN_div".
There's one exception to this rule: meson8b_fclk_div3_div's name is
"fclk_div_div3". It's child clock meson8b_fclk_div3 however references
it as "fclk_div3_div" (following the naming schema explained above).
Fix the naming of the meson8b_fclk_div3_div clock to follow the naming
schema. This also fixes serial console on my Meson8m2 board because
"clk81" uses fclk_div3 as parent. However, since the hierarchy stops at
meson8b_fclk_div3 there's no known parent clock and the rate of "clk81"
and all of it's children (UART clock, SDIO MMC controller clock, ...)
are all 0.
Fixes:
|
||
|---|---|---|
| .. | ||
| axg.c | ||
| axg.h | ||
| clk-audio-divider.c | ||
| clk-mpll.c | ||
| clk-pll.c | ||
| clk-regmap.c | ||
| clk-regmap.h | ||
| clkc.h | ||
| gxbb-aoclk-32k.c | ||
| gxbb-aoclk.c | ||
| gxbb-aoclk.h | ||
| gxbb.c | ||
| gxbb.h | ||
| Kconfig | ||
| Makefile | ||
| meson8b.c | ||
| meson8b.h | ||