forked from Minki/linux
c7baab5d1e
Anders Grafström reports that footbridge fails to build after 1c4a4f4.
Fix this by adding the necessary definitions for __pfn_to_bus and
__bus_to_pfn.
Reported-by: Anders Grafström <anders.grafstrom@netinsight.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
70 lines
1.9 KiB
C
70 lines
1.9 KiB
C
/*
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* arch/arm/mach-footbridge/include/mach/memory.h
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*
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* Copyright (C) 1996-1999 Russell King.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Changelog:
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* 20-Oct-1996 RMK Created
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* 31-Dec-1997 RMK Fixed definitions to reduce warnings.
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* 17-May-1998 DAG Added __virt_to_bus and __bus_to_virt functions.
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* 21-Nov-1998 RMK Changed __virt_to_bus and __bus_to_virt to macros.
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* 21-Mar-1999 RMK Added PAGE_OFFSET for co285 architecture.
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* Renamed to memory.h
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* Moved PAGE_OFFSET and TASK_SIZE here
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*/
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#ifndef __ASM_ARCH_MEMORY_H
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#define __ASM_ARCH_MEMORY_H
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#if defined(CONFIG_FOOTBRIDGE_ADDIN)
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/*
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* If we may be using add-in footbridge mode, then we must
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* use the out-of-line translation that makes use of the
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* PCI BAR
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*/
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#ifndef __ASSEMBLY__
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extern unsigned long __virt_to_bus(unsigned long);
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extern unsigned long __bus_to_virt(unsigned long);
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extern unsigned long __pfn_to_bus(unsigned long);
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extern unsigned long __bus_to_pfn(unsigned long);
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#endif
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#define __virt_to_bus __virt_to_bus
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#define __bus_to_virt __bus_to_virt
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#elif defined(CONFIG_FOOTBRIDGE_HOST)
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/*
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* The footbridge is programmed to expose the system RAM at 0xe0000000.
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* The requirement is that the RAM isn't placed at bus address 0, which
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* would clash with VGA cards.
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*/
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#define BUS_OFFSET 0xe0000000
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#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET))
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#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET))
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#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - PHYS_OFFSET))
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#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - PHYS_OFFSET))
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#else
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#error "Undefined footbridge mode"
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#endif
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/*
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* Cache flushing area.
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*/
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#define FLUSH_BASE 0xf9000000
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/*
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* Physical DRAM offset.
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*/
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#define PHYS_OFFSET UL(0x00000000)
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#define FLUSH_BASE_PHYS 0x50000000
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#endif
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