5a5dfe4b85
Setting up groups can be complicated due to the complicated scheduling
restrictions of different PMUs.
User tools usually don't understand all these restrictions.
Still in many cases it is useful to set up groups and they work most of
the time. However if the group is set up wrong some members will not
report any value because they never get scheduled.
Add a concept of a 'weak group': try to set up a group, but if it's not
schedulable fallback to not using a group. That gives us the best of
both worlds: groups if they work, but still a usable fallback if they
don't.
In theory it would be possible to have more complex fallback strategies
(e.g. try to split the group in half), but the simple fallback of not
using a group seems to work for now.
So far the weak group is only implemented for perf stat, not for record.
Here's an unschedulable group (on IvyBridge with SMT on)
% perf stat -e '{branches,branch-misses,l1d.replacement,l2_lines_in.all,l2_rqsts.all_code_rd}' -a sleep 1
73,806,067 branches
4,848,144 branch-misses # 6.57% of all branches
14,754,458 l1d.replacement
24,905,558 l2_lines_in.all
<not supported> l2_rqsts.all_code_rd <------- will never report anything
With the weak group:
% perf stat -e '{branches,branch-misses,l1d.replacement,l2_lines_in.all,l2_rqsts.all_code_rd}:W' -a sleep 1
125,366,055 branches (80.02%)
9,208,402 branch-misses # 7.35% of all branches (80.01%)
24,560,249 l1d.replacement (80.00%)
43,174,971 l2_lines_in.all (80.05%)
31,891,457 l2_rqsts.all_code_rd (79.92%)
The extra event scheduled with some extra multiplexing
v2: Move fallback code to separate function.
Add comment on for_each_group_member
Adjust to new perf_evsel__close interface
v3: Fix debug print out.
Committer testing:
Before:
# perf stat -e '{branches,branch-misses,l1d.replacement,l2_lines_in.all,l2_rqsts.all_code_rd}' -a sleep 1
Performance counter stats for 'system wide':
<not counted> branches
<not counted> branch-misses
<not counted> l1d.replacement
<not counted> l2_lines_in.all
<not supported> l2_rqsts.all_code_rd
1.002147212 seconds time elapsed
# perf stat -e '{branches,l1d.replacement,l2_lines_in.all,l2_rqsts.all_code_rd}' -a sleep 1
Performance counter stats for 'system wide':
83,207,892 branches
11,065,444 l1d.replacement
28,484,024 l2_lines_in.all
12,186,179 l2_rqsts.all_code_rd
1.001739493 seconds time elapsed
After:
# perf stat -e '{branches,branch-misses,l1d.replacement,l2_lines_in.all,l2_rqsts.all_code_rd}':W -a sleep 1
Performance counter stats for 'system wide':
543,323,909 branches (80.01%)
27,100,512 branch-misses # 4.99% of all branches (80.02%)
50,402,905 l1d.replacement (80.03%)
67,385,892 l2_lines_in.all (80.01%)
21,352,885 l2_rqsts.all_code_rd (79.94%)
1.001086658 seconds time elapsed
#
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Tested-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Link: http://lkml.kernel.org/r/20170831194036.30146-2-andi@firstfloor.org
[ Add a "'perf stat' only, for now" comment in the man page, suggested by Jiri ]
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
271 lines
9.1 KiB
Plaintext
271 lines
9.1 KiB
Plaintext
perf-list(1)
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============
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NAME
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----
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perf-list - List all symbolic event types
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SYNOPSIS
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--------
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[verse]
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'perf list' [--no-desc] [--long-desc] [hw|sw|cache|tracepoint|pmu|sdt|event_glob]
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DESCRIPTION
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-----------
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This command displays the symbolic event types which can be selected in the
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various perf commands with the -e option.
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OPTIONS
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-------
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--no-desc::
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Don't print descriptions.
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-v::
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--long-desc::
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Print longer event descriptions.
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--details::
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Print how named events are resolved internally into perf events, and also
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any extra expressions computed by perf stat.
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[[EVENT_MODIFIERS]]
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EVENT MODIFIERS
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---------------
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Events can optionally have a modifier by appending a colon and one or
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more modifiers. Modifiers allow the user to restrict the events to be
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counted. The following modifiers exist:
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u - user-space counting
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k - kernel counting
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h - hypervisor counting
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I - non idle counting
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G - guest counting (in KVM guests)
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H - host counting (not in KVM guests)
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p - precise level
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P - use maximum detected precise level
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S - read sample value (PERF_SAMPLE_READ)
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D - pin the event to the PMU
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W - group is weak and will fallback to non-group if not schedulable,
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only supported in 'perf stat' for now.
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The 'p' modifier can be used for specifying how precise the instruction
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address should be. The 'p' modifier can be specified multiple times:
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0 - SAMPLE_IP can have arbitrary skid
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1 - SAMPLE_IP must have constant skid
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2 - SAMPLE_IP requested to have 0 skid
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3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid
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sample shadowing effects.
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For Intel systems precise event sampling is implemented with PEBS
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which supports up to precise-level 2, and precise level 3 for
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some special cases
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On AMD systems it is implemented using IBS (up to precise-level 2).
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The precise modifier works with event types 0x76 (cpu-cycles, CPU
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clocks not halted) and 0xC1 (micro-ops retired). Both events map to
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IBS execution sampling (IBS op) with the IBS Op Counter Control bit
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(IbsOpCntCtl) set respectively (see AMD64 Architecture Programmer’s
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Manual Volume 2: System Programming, 13.3 Instruction-Based
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Sampling). Examples to use IBS:
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perf record -a -e cpu-cycles:p ... # use ibs op counting cycles
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perf record -a -e r076:p ... # same as -e cpu-cycles:p
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perf record -a -e r0C1:p ... # use ibs op counting micro-ops
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RAW HARDWARE EVENT DESCRIPTOR
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-----------------------------
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Even when an event is not available in a symbolic form within perf right now,
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it can be encoded in a per processor specific way.
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For instance For x86 CPUs NNN represents the raw register encoding with the
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layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout
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of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344,
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Figure 13-7 Performance Event-Select Register (PerfEvtSeln)).
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Note: Only the following bit fields can be set in x86 counter
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registers: event, umask, edge, inv, cmask. Esp. guest/host only and
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OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT
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MODIFIERS>>.
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Example:
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If the Intel docs for a QM720 Core i7 describe an event as:
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Event Umask Event Mask
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Num. Value Mnemonic Description Comment
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A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and
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delivered by loop stream detector invert to count
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cycles
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raw encoding of 0x1A8 can be used:
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perf stat -e r1a8 -a sleep 1
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perf record -e r1a8 ...
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You should refer to the processor specific documentation for getting these
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details. Some of them are referenced in the SEE ALSO section below.
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ARBITRARY PMUS
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--------------
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perf also supports an extended syntax for specifying raw parameters
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to PMUs. Using this typically requires looking up the specific event
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in the CPU vendor specific documentation.
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The available PMUs and their raw parameters can be listed with
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ls /sys/devices/*/format
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For example the raw event "LSD.UOPS" core pmu event above could
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be specified as
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perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=1/ ...
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PER SOCKET PMUS
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---------------
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Some PMUs are not associated with a core, but with a whole CPU socket.
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Events on these PMUs generally cannot be sampled, but only counted globally
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with perf stat -a. They can be bound to one logical CPU, but will measure
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all the CPUs in the same socket.
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This example measures memory bandwidth every second
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on the first memory controller on socket 0 of a Intel Xeon system
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perf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ...
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Each memory controller has its own PMU. Measuring the complete system
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bandwidth would require specifying all imc PMUs (see perf list output),
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and adding the values together.
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This example measures the combined core power every second
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perf stat -I 1000 -e power/energy-cores/ -a
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ACCESS RESTRICTIONS
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-------------------
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For non root users generally only context switched PMU events are available.
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This is normally only the events in the cpu PMU, the predefined events
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like cycles and instructions and some software events.
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Other PMUs and global measurements are normally root only.
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Some event qualifiers, such as "any", are also root only.
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This can be overriden by setting the kernel.perf_event_paranoid
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sysctl to -1, which allows non root to use these events.
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For accessing trace point events perf needs to have read access to
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/sys/kernel/debug/tracing, even when perf_event_paranoid is in a relaxed
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setting.
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TRACING
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-------
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Some PMUs control advanced hardware tracing capabilities, such as Intel PT,
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that allows low overhead execution tracing. These are described in a separate
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intel-pt.txt document.
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PARAMETERIZED EVENTS
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--------------------
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Some pmu events listed by 'perf-list' will be displayed with '?' in them. For
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example:
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hv_gpci/dtbp_ptitc,phys_processor_idx=?/
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This means that when provided as an event, a value for '?' must
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also be supplied. For example:
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perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ...
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EVENT GROUPS
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------------
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Perf supports time based multiplexing of events, when the number of events
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active exceeds the number of hardware performance counters. Multiplexing
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can cause measurement errors when the workload changes its execution
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profile.
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When metrics are computed using formulas from event counts, it is useful to
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ensure some events are always measured together as a group to minimize multiplexing
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errors. Event groups can be specified using { }.
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perf stat -e '{instructions,cycles}' ...
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The number of available performance counters depend on the CPU. A group
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cannot contain more events than available counters.
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For example Intel Core CPUs typically have four generic performance counters
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for the core, plus three fixed counters for instructions, cycles and
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ref-cycles. Some special events have restrictions on which counter they
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can schedule, and may not support multiple instances in a single group.
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When too many events are specified in the group none of them will not
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be measured.
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Globally pinned events can limit the number of counters available for
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other groups. On x86 systems, the NMI watchdog pins a counter by default.
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The nmi watchdog can be disabled as root with
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echo 0 > /proc/sys/kernel/nmi_watchdog
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Events from multiple different PMUs cannot be mixed in a group, with
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some exceptions for software events.
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LEADER SAMPLING
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---------------
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perf also supports group leader sampling using the :S specifier.
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perf record -e '{cycles,instructions}:S' ...
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perf report --group
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Normally all events in a event group sample, but with :S only
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the first event (the leader) samples, and it only reads the values of the
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other events in the group.
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OPTIONS
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-------
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Without options all known events will be listed.
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To limit the list use:
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. 'hw' or 'hardware' to list hardware events such as cache-misses, etc.
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. 'sw' or 'software' to list software events such as context switches, etc.
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. 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc.
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. 'tracepoint' to list all tracepoint events, alternatively use
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'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched,
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block, etc.
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. 'pmu' to print the kernel supplied PMU events.
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. 'sdt' to list all Statically Defined Tracepoint events.
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. If none of the above is matched, it will apply the supplied glob to all
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events, printing the ones that match.
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. As a last resort, it will do a substring search in all event names.
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One or more types can be used at the same time, listing the events for the
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types specified.
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Support raw format:
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. '--raw-dump', shows the raw-dump of all the events.
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. '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of
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a certain kind of events.
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SEE ALSO
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--------
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linkperf:perf-stat[1], linkperf:perf-top[1],
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linkperf:perf-record[1],
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http://www.intel.com/sdm/[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide],
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http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming]
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