forked from Minki/linux
b1526421ea
cx18: Create cx18_ specific wrappers for all pci mmio accessesors. This is a first step in instrumenting all CX23418 PCI bus IO, to debug problems with accessing the CX23418's PCI memory mapped IO. Signed-off-by: Andy Walls <awalls@radix.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
214 lines
5.9 KiB
C
214 lines
5.9 KiB
C
/*
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* cx18 gpio functions
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*
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* Derived from ivtv-gpio.c
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*
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* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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* 02111-1307 USA
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*/
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#include "cx18-driver.h"
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#include "cx18-io.h"
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#include "cx18-cards.h"
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#include "cx18-gpio.h"
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#include "tuner-xc2028.h"
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/********************* GPIO stuffs *********************/
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/* GPIO registers */
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#define CX18_REG_GPIO_IN 0xc72010
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#define CX18_REG_GPIO_OUT1 0xc78100
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#define CX18_REG_GPIO_DIR1 0xc78108
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#define CX18_REG_GPIO_OUT2 0xc78104
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#define CX18_REG_GPIO_DIR2 0xc7810c
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/*
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* HVR-1600 GPIO pins, courtesy of Hauppauge:
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*
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* gpio0: zilog ir process reset pin
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* gpio1: zilog programming pin (you should never use this)
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* gpio12: cx24227 reset pin
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* gpio13: cs5345 reset pin
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*/
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static void gpio_write(struct cx18 *cx)
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{
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u32 dir = cx->gpio_dir;
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u32 val = cx->gpio_val;
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cx18_write_reg(cx, (dir & 0xffff) << 16, CX18_REG_GPIO_DIR1);
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cx18_write_reg(cx, ((dir & 0xffff) << 16) | (val & 0xffff),
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CX18_REG_GPIO_OUT1);
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cx18_write_reg(cx, dir & 0xffff0000, CX18_REG_GPIO_DIR2);
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cx18_write_reg_sync(cx, (dir & 0xffff0000) | ((val & 0xffff0000) >> 16),
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CX18_REG_GPIO_OUT2);
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}
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void cx18_reset_i2c_slaves_gpio(struct cx18 *cx)
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{
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const struct cx18_gpio_i2c_slave_reset *p;
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p = &cx->card->gpio_i2c_slave_reset;
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if ((p->active_lo_mask | p->active_hi_mask) == 0)
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return;
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/* Assuming that the masks are a subset of the bits in gpio_dir */
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/* Assert */
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mutex_lock(&cx->gpio_lock);
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cx->gpio_val =
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(cx->gpio_val | p->active_hi_mask) & ~(p->active_lo_mask);
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gpio_write(cx);
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schedule_timeout_uninterruptible(msecs_to_jiffies(p->msecs_asserted));
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/* Deassert */
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cx->gpio_val =
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(cx->gpio_val | p->active_lo_mask) & ~(p->active_hi_mask);
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gpio_write(cx);
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schedule_timeout_uninterruptible(msecs_to_jiffies(p->msecs_recovery));
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mutex_unlock(&cx->gpio_lock);
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}
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void cx18_reset_ir_gpio(void *data)
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{
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struct cx18 *cx = ((struct cx18_i2c_algo_callback_data *)data)->cx;
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const struct cx18_gpio_i2c_slave_reset *p;
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p = &cx->card->gpio_i2c_slave_reset;
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if (p->ir_reset_mask == 0)
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return;
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CX18_DEBUG_INFO("Resetting IR microcontroller\n");
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/*
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Assert timing for the Z8F0811 on HVR-1600 boards:
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1. Assert RESET for min of 4 clock cycles at 18.432 MHz to initiate
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2. Reset then takes 66 WDT cycles at 10 kHz + 16 xtal clock cycles
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(6,601,085 nanoseconds ~= 7 milliseconds)
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3. DBG pin must be high before chip exits reset for normal operation.
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DBG is open drain and hopefully pulled high since we don't
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normally drive it (GPIO 1?) for the HVR-1600
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4. Z8F0811 won't exit reset until RESET is deasserted
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*/
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mutex_lock(&cx->gpio_lock);
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cx->gpio_val = cx->gpio_val & ~p->ir_reset_mask;
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gpio_write(cx);
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mutex_unlock(&cx->gpio_lock);
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schedule_timeout_uninterruptible(msecs_to_jiffies(p->msecs_asserted));
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/*
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Zilog comes out of reset, loads reset vector address and executes
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from there. Required recovery delay unknown.
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*/
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mutex_lock(&cx->gpio_lock);
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cx->gpio_val = cx->gpio_val | p->ir_reset_mask;
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gpio_write(cx);
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mutex_unlock(&cx->gpio_lock);
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schedule_timeout_uninterruptible(msecs_to_jiffies(p->msecs_recovery));
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}
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EXPORT_SYMBOL(cx18_reset_ir_gpio);
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/* This symbol is exported for use by an infrared module for the IR-blaster */
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void cx18_gpio_init(struct cx18 *cx)
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{
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mutex_lock(&cx->gpio_lock);
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cx->gpio_dir = cx->card->gpio_init.direction;
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cx->gpio_val = cx->card->gpio_init.initial_value;
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if (cx->card->tuners[0].tuner == TUNER_XC2028) {
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cx->gpio_dir |= 1 << cx->card->xceive_pin;
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cx->gpio_val |= 1 << cx->card->xceive_pin;
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}
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if (cx->gpio_dir == 0) {
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mutex_unlock(&cx->gpio_lock);
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return;
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}
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CX18_DEBUG_INFO("GPIO initial dir: %08x/%08x out: %08x/%08x\n",
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cx18_read_reg(cx, CX18_REG_GPIO_DIR1),
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cx18_read_reg(cx, CX18_REG_GPIO_DIR2),
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cx18_read_reg(cx, CX18_REG_GPIO_OUT1),
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cx18_read_reg(cx, CX18_REG_GPIO_OUT2));
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gpio_write(cx);
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mutex_unlock(&cx->gpio_lock);
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}
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/* Xceive tuner reset function */
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int cx18_reset_tuner_gpio(void *dev, int cmd, int value)
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{
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struct i2c_algo_bit_data *algo = dev;
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struct cx18_i2c_algo_callback_data *cb_data = algo->data;
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struct cx18 *cx = cb_data->cx;
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if (cmd != XC2028_TUNER_RESET)
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return 0;
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CX18_DEBUG_INFO("Resetting tuner\n");
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mutex_lock(&cx->gpio_lock);
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cx->gpio_val &= ~(1 << cx->card->xceive_pin);
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gpio_write(cx);
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mutex_unlock(&cx->gpio_lock);
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schedule_timeout_interruptible(msecs_to_jiffies(1));
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mutex_lock(&cx->gpio_lock);
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cx->gpio_val |= 1 << cx->card->xceive_pin;
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gpio_write(cx);
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mutex_unlock(&cx->gpio_lock);
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schedule_timeout_interruptible(msecs_to_jiffies(1));
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return 0;
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}
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int cx18_gpio(struct cx18 *cx, unsigned int command, void *arg)
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{
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struct v4l2_routing *route = arg;
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u32 mask, data;
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switch (command) {
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case VIDIOC_INT_S_AUDIO_ROUTING:
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if (route->input > 2)
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return -EINVAL;
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mask = cx->card->gpio_audio_input.mask;
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switch (route->input) {
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case 0:
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data = cx->card->gpio_audio_input.tuner;
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break;
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case 1:
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data = cx->card->gpio_audio_input.linein;
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break;
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case 2:
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default:
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data = cx->card->gpio_audio_input.radio;
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break;
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}
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break;
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default:
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return -EINVAL;
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}
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if (mask) {
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mutex_lock(&cx->gpio_lock);
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cx->gpio_val = (cx->gpio_val & ~mask) | (data & mask);
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gpio_write(cx);
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mutex_unlock(&cx->gpio_lock);
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}
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return 0;
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}
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