forked from Minki/linux
ca4e419c20
Conflicts: arch/arm/plat-mxc/avic.c arch/arm/plat-mxc/include/mach/common.h Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
113 lines
3.9 KiB
C
113 lines
3.9 KiB
C
#ifndef __MACH_MX25_H__
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#define __MACH_MX25_H__
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#define MX25_AIPS1_BASE_ADDR 0x43f00000
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#define MX25_AIPS1_SIZE SZ_1M
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#define MX25_AIPS2_BASE_ADDR 0x53f00000
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#define MX25_AIPS2_SIZE SZ_1M
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#define MX25_AVIC_BASE_ADDR 0x68000000
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#define MX25_AVIC_SIZE SZ_1M
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#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000)
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#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000)
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#define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000)
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#define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000)
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#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000)
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#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000)
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#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
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#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
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#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000)
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#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000)
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#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000)
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#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000)
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#define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000)
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#define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000)
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#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000)
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#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000)
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#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000)
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#define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000)
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#define MX25_UART1_BASE_ADDR 0x43f90000
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#define MX25_UART2_BASE_ADDR 0x43f94000
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#define MX25_AUDMUX_BASE_ADDR 0x43fb0000
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#define MX25_UART3_BASE_ADDR 0x5000c000
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#define MX25_UART4_BASE_ADDR 0x50008000
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#define MX25_UART5_BASE_ADDR 0x5002c000
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#define MX25_CSPI3_BASE_ADDR 0x50004000
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#define MX25_CSPI2_BASE_ADDR 0x50010000
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#define MX25_FEC_BASE_ADDR 0x50038000
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#define MX25_SSI2_BASE_ADDR 0x50014000
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#define MX25_SSI1_BASE_ADDR 0x50034000
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#define MX25_NFC_BASE_ADDR 0xbb000000
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#define MX25_IIM_BASE_ADDR 0x53ff0000
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#define MX25_DRYICE_BASE_ADDR 0x53ffc000
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#define MX25_ESDHC1_BASE_ADDR 0x53fb4000
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#define MX25_ESDHC2_BASE_ADDR 0x53fb8000
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#define MX25_LCDC_BASE_ADDR 0x53fbc000
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#define MX25_KPP_BASE_ADDR 0x43fa8000
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#define MX25_SDMA_BASE_ADDR 0x53fd4000
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#define MX25_USB_BASE_ADDR 0x53ff4000
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#define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000)
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/*
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* The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200
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* for the host controller. Early documentation drafts specified 0x400 and
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* Freescale internal sources confirm only the latter value to work.
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*/
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#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400)
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#define MX25_CSI_BASE_ADDR 0x53ff8000
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#define MX25_IO_P2V(x) IMX_IO_P2V(x)
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#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x))
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#define MX25_INT_CSPI3 0
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#define MX25_INT_I2C1 3
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#define MX25_INT_I2C2 4
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#define MX25_INT_UART4 5
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#define MX25_INT_ESDHC2 8
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#define MX25_INT_ESDHC1 9
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#define MX25_INT_I2C3 10
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#define MX25_INT_SSI2 11
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#define MX25_INT_SSI1 12
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#define MX25_INT_CSPI2 13
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#define MX25_INT_CSPI1 14
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#define MX25_INT_GPIO3 16
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#define MX25_INT_CSI 17
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#define MX25_INT_UART3 18
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#define MX25_INT_GPIO4 23
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#define MX25_INT_KPP 24
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#define MX25_INT_DRYICE 25
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#define MX25_INT_PWM1 26
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#define MX25_INT_UART2 32
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#define MX25_INT_NFC 33
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#define MX25_INT_SDMA 34
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#define MX25_INT_USB_HS 35
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#define MX25_INT_PWM2 36
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#define MX25_INT_USB_OTG 37
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#define MX25_INT_LCDC 39
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#define MX25_INT_UART5 40
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#define MX25_INT_PWM3 41
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#define MX25_INT_PWM4 42
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#define MX25_INT_CAN1 43
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#define MX25_INT_CAN2 44
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#define MX25_INT_UART1 45
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#define MX25_INT_GPIO2 51
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#define MX25_INT_GPIO1 52
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#define MX25_INT_FEC 57
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#define MX25_DMA_REQ_SSI2_RX1 22
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#define MX25_DMA_REQ_SSI2_TX1 23
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#define MX25_DMA_REQ_SSI2_RX0 24
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#define MX25_DMA_REQ_SSI2_TX0 25
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#define MX25_DMA_REQ_SSI1_RX1 26
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#define MX25_DMA_REQ_SSI1_TX1 27
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#define MX25_DMA_REQ_SSI1_RX0 28
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#define MX25_DMA_REQ_SSI1_TX0 29
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#ifndef __ASSEMBLY__
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extern int mx25_revision(void);
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#endif
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#endif /* ifndef __MACH_MX25_H__ */
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