forked from Minki/linux
92fd65c095
Signed-off-by: Saurav Kashyap <saurav.kashyap@qlogic.com> Signed-off-by: Giridhar Malavali <giridhar.malavali@qlogic.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
1905 lines
58 KiB
C
1905 lines
58 KiB
C
/*
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* QLogic Fibre Channel HBA Driver
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* Copyright (c) 2003-2011 QLogic Corporation
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*
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* See LICENSE.qla2xxx for copyright and licensing details.
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*/
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/*
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* Table for showing the current message id in use for particular level
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* Change this table for addition of log/debug messages.
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* -----------------------------------------------------
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* | Level | Last Value Used |
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* -----------------------------------------------------
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* | Module Init and Probe | 0x0116 |
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* | Mailbox commands | 0x111e |
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* | Device Discovery | 0x2083 |
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* | Queue Command and IO tracing | 0x302e |
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* | DPC Thread | 0x401c |
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* | Async Events | 0x5059 |
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* | Timer Routines | 0x600d |
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* | User Space Interactions | 0x709c |
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* | Task Management | 0x8043 |
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* | AER/EEH | 0x900f |
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* | Virtual Port | 0xa007 |
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* | ISP82XX Specific | 0xb027 |
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* | MultiQ | 0xc00b |
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* | Misc | 0xd00b |
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* -----------------------------------------------------
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*/
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#include "qla_def.h"
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#include <linux/delay.h>
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static uint32_t ql_dbg_offset = 0x800;
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static inline void
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qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump)
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{
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fw_dump->fw_major_version = htonl(ha->fw_major_version);
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fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
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fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
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fw_dump->fw_attributes = htonl(ha->fw_attributes);
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fw_dump->vendor = htonl(ha->pdev->vendor);
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fw_dump->device = htonl(ha->pdev->device);
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fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
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fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
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}
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static inline void *
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qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr)
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{
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struct req_que *req = ha->req_q_map[0];
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struct rsp_que *rsp = ha->rsp_q_map[0];
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/* Request queue. */
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memcpy(ptr, req->ring, req->length *
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sizeof(request_t));
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/* Response queue. */
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ptr += req->length * sizeof(request_t);
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memcpy(ptr, rsp->ring, rsp->length *
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sizeof(response_t));
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return ptr + (rsp->length * sizeof(response_t));
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}
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static int
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qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
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uint32_t ram_dwords, void **nxt)
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{
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int rval;
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uint32_t cnt, stat, timer, dwords, idx;
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uint16_t mb0;
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struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
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dma_addr_t dump_dma = ha->gid_list_dma;
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uint32_t *dump = (uint32_t *)ha->gid_list;
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rval = QLA_SUCCESS;
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mb0 = 0;
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WRT_REG_WORD(®->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
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clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
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dwords = GID_LIST_SIZE / 4;
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for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
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cnt += dwords, addr += dwords) {
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if (cnt + dwords > ram_dwords)
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dwords = ram_dwords - cnt;
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WRT_REG_WORD(®->mailbox1, LSW(addr));
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WRT_REG_WORD(®->mailbox8, MSW(addr));
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WRT_REG_WORD(®->mailbox2, MSW(dump_dma));
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WRT_REG_WORD(®->mailbox3, LSW(dump_dma));
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WRT_REG_WORD(®->mailbox6, MSW(MSD(dump_dma)));
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WRT_REG_WORD(®->mailbox7, LSW(MSD(dump_dma)));
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WRT_REG_WORD(®->mailbox4, MSW(dwords));
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WRT_REG_WORD(®->mailbox5, LSW(dwords));
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WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT);
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for (timer = 6000000; timer; timer--) {
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/* Check for pending interrupts. */
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stat = RD_REG_DWORD(®->host_status);
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if (stat & HSRX_RISC_INT) {
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stat &= 0xff;
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if (stat == 0x1 || stat == 0x2 ||
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stat == 0x10 || stat == 0x11) {
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set_bit(MBX_INTERRUPT,
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&ha->mbx_cmd_flags);
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mb0 = RD_REG_WORD(®->mailbox0);
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WRT_REG_DWORD(®->hccr,
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HCCRX_CLR_RISC_INT);
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RD_REG_DWORD(®->hccr);
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break;
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}
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/* Clear this intr; it wasn't a mailbox intr */
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WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT);
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RD_REG_DWORD(®->hccr);
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}
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udelay(5);
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}
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if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
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rval = mb0 & MBS_MASK;
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for (idx = 0; idx < dwords; idx++)
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ram[cnt + idx] = swab32(dump[idx]);
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} else {
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rval = QLA_FUNCTION_FAILED;
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}
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}
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*nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
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return rval;
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}
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static int
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qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram,
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uint32_t cram_size, void **nxt)
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{
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int rval;
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/* Code RAM. */
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rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
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if (rval != QLA_SUCCESS)
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return rval;
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/* External Memory. */
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return qla24xx_dump_ram(ha, 0x100000, *nxt,
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ha->fw_memory_size - 0x100000 + 1, nxt);
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}
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static uint32_t *
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qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
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uint32_t count, uint32_t *buf)
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{
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uint32_t __iomem *dmp_reg;
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WRT_REG_DWORD(®->iobase_addr, iobase);
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dmp_reg = ®->iobase_window;
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while (count--)
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*buf++ = htonl(RD_REG_DWORD(dmp_reg++));
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return buf;
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}
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static inline int
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qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
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{
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int rval = QLA_SUCCESS;
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uint32_t cnt;
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WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE);
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for (cnt = 30000;
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((RD_REG_DWORD(®->host_status) & HSRX_RISC_PAUSED) == 0) &&
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rval == QLA_SUCCESS; cnt--) {
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if (cnt)
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udelay(100);
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else
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rval = QLA_FUNCTION_TIMEOUT;
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}
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return rval;
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}
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static int
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qla24xx_soft_reset(struct qla_hw_data *ha)
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{
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int rval = QLA_SUCCESS;
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uint32_t cnt;
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uint16_t mb0, wd;
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struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
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/* Reset RISC. */
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WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
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for (cnt = 0; cnt < 30000; cnt++) {
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if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
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break;
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udelay(10);
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}
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WRT_REG_DWORD(®->ctrl_status,
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CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
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pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
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udelay(100);
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/* Wait for firmware to complete NVRAM accesses. */
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mb0 = (uint32_t) RD_REG_WORD(®->mailbox0);
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for (cnt = 10000 ; cnt && mb0; cnt--) {
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udelay(5);
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mb0 = (uint32_t) RD_REG_WORD(®->mailbox0);
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barrier();
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}
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/* Wait for soft-reset to complete. */
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for (cnt = 0; cnt < 30000; cnt++) {
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if ((RD_REG_DWORD(®->ctrl_status) &
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CSRX_ISP_SOFT_RESET) == 0)
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break;
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udelay(10);
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}
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WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET);
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RD_REG_DWORD(®->hccr); /* PCI Posting. */
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for (cnt = 30000; RD_REG_WORD(®->mailbox0) != 0 &&
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rval == QLA_SUCCESS; cnt--) {
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if (cnt)
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udelay(100);
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else
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rval = QLA_FUNCTION_TIMEOUT;
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}
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return rval;
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}
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static int
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qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram,
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uint32_t ram_words, void **nxt)
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{
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int rval;
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uint32_t cnt, stat, timer, words, idx;
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uint16_t mb0;
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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dma_addr_t dump_dma = ha->gid_list_dma;
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uint16_t *dump = (uint16_t *)ha->gid_list;
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rval = QLA_SUCCESS;
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mb0 = 0;
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WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
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clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
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words = GID_LIST_SIZE / 2;
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for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
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cnt += words, addr += words) {
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if (cnt + words > ram_words)
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words = ram_words - cnt;
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WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
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WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
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WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
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WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
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WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
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WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
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WRT_MAILBOX_REG(ha, reg, 4, words);
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WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT);
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for (timer = 6000000; timer; timer--) {
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/* Check for pending interrupts. */
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stat = RD_REG_DWORD(®->u.isp2300.host_status);
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if (stat & HSR_RISC_INT) {
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stat &= 0xff;
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if (stat == 0x1 || stat == 0x2) {
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set_bit(MBX_INTERRUPT,
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&ha->mbx_cmd_flags);
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mb0 = RD_MAILBOX_REG(ha, reg, 0);
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/* Release mailbox registers. */
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WRT_REG_WORD(®->semaphore, 0);
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WRT_REG_WORD(®->hccr,
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HCCR_CLR_RISC_INT);
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RD_REG_WORD(®->hccr);
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break;
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} else if (stat == 0x10 || stat == 0x11) {
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set_bit(MBX_INTERRUPT,
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&ha->mbx_cmd_flags);
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mb0 = RD_MAILBOX_REG(ha, reg, 0);
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WRT_REG_WORD(®->hccr,
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HCCR_CLR_RISC_INT);
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RD_REG_WORD(®->hccr);
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break;
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}
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/* clear this intr; it wasn't a mailbox intr */
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WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
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RD_REG_WORD(®->hccr);
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}
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udelay(5);
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}
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if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
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rval = mb0 & MBS_MASK;
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for (idx = 0; idx < words; idx++)
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ram[cnt + idx] = swab16(dump[idx]);
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} else {
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rval = QLA_FUNCTION_FAILED;
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}
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}
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*nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
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return rval;
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}
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static inline void
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qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
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uint16_t *buf)
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{
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uint16_t __iomem *dmp_reg = ®->u.isp2300.fb_cmd;
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while (count--)
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*buf++ = htons(RD_REG_WORD(dmp_reg++));
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}
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static inline void *
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qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr)
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{
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if (!ha->eft)
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return ptr;
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memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
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return ptr + ntohl(ha->fw_dump->eft_size);
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}
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static inline void *
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qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
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{
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uint32_t cnt;
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uint32_t *iter_reg;
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struct qla2xxx_fce_chain *fcec = ptr;
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if (!ha->fce)
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return ptr;
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*last_chain = &fcec->type;
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fcec->type = __constant_htonl(DUMP_CHAIN_FCE);
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fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
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fce_calc_size(ha->fce_bufs));
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fcec->size = htonl(fce_calc_size(ha->fce_bufs));
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fcec->addr_l = htonl(LSD(ha->fce_dma));
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fcec->addr_h = htonl(MSD(ha->fce_dma));
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iter_reg = fcec->eregs;
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for (cnt = 0; cnt < 8; cnt++)
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*iter_reg++ = htonl(ha->fce_mb[cnt]);
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memcpy(iter_reg, ha->fce, ntohl(fcec->size));
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return iter_reg;
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}
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static inline void *
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qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
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{
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uint32_t cnt, que_idx;
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uint8_t que_cnt;
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struct qla2xxx_mq_chain *mq = ptr;
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struct device_reg_25xxmq __iomem *reg;
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if (!ha->mqenable)
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return ptr;
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mq = ptr;
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*last_chain = &mq->type;
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mq->type = __constant_htonl(DUMP_CHAIN_MQ);
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mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain));
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que_cnt = ha->max_req_queues > ha->max_rsp_queues ?
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ha->max_req_queues : ha->max_rsp_queues;
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mq->count = htonl(que_cnt);
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for (cnt = 0; cnt < que_cnt; cnt++) {
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reg = (struct device_reg_25xxmq *) ((void *)
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ha->mqiobase + cnt * QLA_QUE_PAGE);
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que_idx = cnt * 4;
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mq->qregs[que_idx] = htonl(RD_REG_DWORD(®->req_q_in));
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mq->qregs[que_idx+1] = htonl(RD_REG_DWORD(®->req_q_out));
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mq->qregs[que_idx+2] = htonl(RD_REG_DWORD(®->rsp_q_in));
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mq->qregs[que_idx+3] = htonl(RD_REG_DWORD(®->rsp_q_out));
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}
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return ptr + sizeof(struct qla2xxx_mq_chain);
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}
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static void
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qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval)
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{
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struct qla_hw_data *ha = vha->hw;
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if (rval != QLA_SUCCESS) {
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ql_log(ql_log_warn, vha, 0xd000,
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"Failed to dump firmware (%x).\n", rval);
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ha->fw_dumped = 0;
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} else {
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ql_log(ql_log_info, vha, 0xd001,
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"Firmware dump saved to temp buffer (%ld/%p).\n",
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vha->host_no, ha->fw_dump);
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ha->fw_dumped = 1;
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qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
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}
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}
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/**
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* qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
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* @ha: HA context
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* @hardware_locked: Called with the hardware_lock
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*/
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void
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qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
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{
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int rval;
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uint32_t cnt;
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struct qla_hw_data *ha = vha->hw;
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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uint16_t __iomem *dmp_reg;
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unsigned long flags;
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struct qla2300_fw_dump *fw;
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void *nxt;
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struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
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flags = 0;
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if (!hardware_locked)
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spin_lock_irqsave(&ha->hardware_lock, flags);
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if (!ha->fw_dump) {
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ql_log(ql_log_warn, vha, 0xd002,
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"No buffer available for dump.\n");
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goto qla2300_fw_dump_failed;
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}
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if (ha->fw_dumped) {
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ql_log(ql_log_warn, vha, 0xd003,
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"Firmware has been previously dumped (%p) "
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"-- ignoring request.\n",
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ha->fw_dump);
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goto qla2300_fw_dump_failed;
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}
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fw = &ha->fw_dump->isp.isp23;
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|
qla2xxx_prep_dump(ha, ha->fw_dump);
|
|
|
|
rval = QLA_SUCCESS;
|
|
fw->hccr = htons(RD_REG_WORD(®->hccr));
|
|
|
|
/* Pause RISC. */
|
|
WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
|
|
if (IS_QLA2300(ha)) {
|
|
for (cnt = 30000;
|
|
(RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 &&
|
|
rval == QLA_SUCCESS; cnt--) {
|
|
if (cnt)
|
|
udelay(100);
|
|
else
|
|
rval = QLA_FUNCTION_TIMEOUT;
|
|
}
|
|
} else {
|
|
RD_REG_WORD(®->hccr); /* PCI Posting. */
|
|
udelay(10);
|
|
}
|
|
|
|
if (rval == QLA_SUCCESS) {
|
|
dmp_reg = ®->flash_address;
|
|
for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
|
|
fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
|
|
|
|
dmp_reg = ®->u.isp2300.req_q_in;
|
|
for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
|
|
fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
|
|
|
|
dmp_reg = ®->u.isp2300.mailbox0;
|
|
for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
|
|
fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
|
|
|
|
WRT_REG_WORD(®->ctrl_status, 0x40);
|
|
qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
|
|
|
|
WRT_REG_WORD(®->ctrl_status, 0x50);
|
|
qla2xxx_read_window(reg, 48, fw->dma_reg);
|
|
|
|
WRT_REG_WORD(®->ctrl_status, 0x00);
|
|
dmp_reg = ®->risc_hw;
|
|
for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
|
|
fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
|
|
|
|
WRT_REG_WORD(®->pcr, 0x2000);
|
|
qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
|
|
|
|
WRT_REG_WORD(®->pcr, 0x2200);
|
|
qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
|
|
|
|
WRT_REG_WORD(®->pcr, 0x2400);
|
|
qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
|
|
|
|
WRT_REG_WORD(®->pcr, 0x2600);
|
|
qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
|
|
|
|
WRT_REG_WORD(®->pcr, 0x2800);
|
|
qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
|
|
|
|
WRT_REG_WORD(®->pcr, 0x2A00);
|
|
qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
|
|
|
|
WRT_REG_WORD(®->pcr, 0x2C00);
|
|
qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
|
|
|
|
WRT_REG_WORD(®->pcr, 0x2E00);
|
|
qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
|
|
|
|
WRT_REG_WORD(®->ctrl_status, 0x10);
|
|
qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
|
|
|
|
WRT_REG_WORD(®->ctrl_status, 0x20);
|
|
qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
|
|
|
|
WRT_REG_WORD(®->ctrl_status, 0x30);
|
|
qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
|
|
|
|
/* Reset RISC. */
|
|
WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET);
|
|
for (cnt = 0; cnt < 30000; cnt++) {
|
|
if ((RD_REG_WORD(®->ctrl_status) &
|
|
CSR_ISP_SOFT_RESET) == 0)
|
|
break;
|
|
|
|
udelay(10);
|
|
}
|
|
}
|
|
|
|
if (!IS_QLA2300(ha)) {
|
|
for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
|
|
rval == QLA_SUCCESS; cnt--) {
|
|
if (cnt)
|
|
udelay(100);
|
|
else
|
|
rval = QLA_FUNCTION_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Get RISC SRAM. */
|
|
if (rval == QLA_SUCCESS)
|
|
rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
|
|
sizeof(fw->risc_ram) / 2, &nxt);
|
|
|
|
/* Get stack SRAM. */
|
|
if (rval == QLA_SUCCESS)
|
|
rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
|
|
sizeof(fw->stack_ram) / 2, &nxt);
|
|
|
|
/* Get data SRAM. */
|
|
if (rval == QLA_SUCCESS)
|
|
rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
|
|
ha->fw_memory_size - 0x11000 + 1, &nxt);
|
|
|
|
if (rval == QLA_SUCCESS)
|
|
qla2xxx_copy_queues(ha, nxt);
|
|
|
|
qla2xxx_dump_post_process(base_vha, rval);
|
|
|
|
qla2300_fw_dump_failed:
|
|
if (!hardware_locked)
|
|
spin_unlock_irqrestore(&ha->hardware_lock, flags);
|
|
}
|
|
|
|
/**
|
|
* qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
|
|
* @ha: HA context
|
|
* @hardware_locked: Called with the hardware_lock
|
|
*/
|
|
void
|
|
qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
|
|
{
|
|
int rval;
|
|
uint32_t cnt, timer;
|
|
uint16_t risc_address;
|
|
uint16_t mb0, mb2;
|
|
struct qla_hw_data *ha = vha->hw;
|
|
struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
|
|
uint16_t __iomem *dmp_reg;
|
|
unsigned long flags;
|
|
struct qla2100_fw_dump *fw;
|
|
struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
|
|
|
|
risc_address = 0;
|
|
mb0 = mb2 = 0;
|
|
flags = 0;
|
|
|
|
if (!hardware_locked)
|
|
spin_lock_irqsave(&ha->hardware_lock, flags);
|
|
|
|
if (!ha->fw_dump) {
|
|
ql_log(ql_log_warn, vha, 0xd004,
|
|
"No buffer available for dump.\n");
|
|
goto qla2100_fw_dump_failed;
|
|
}
|
|
|
|
if (ha->fw_dumped) {
|
|
ql_log(ql_log_warn, vha, 0xd005,
|
|
"Firmware has been previously dumped (%p) "
|
|
"-- ignoring request.\n",
|
|
ha->fw_dump);
|
|
goto qla2100_fw_dump_failed;
|
|
}
|
|
fw = &ha->fw_dump->isp.isp21;
|
|
qla2xxx_prep_dump(ha, ha->fw_dump);
|
|
|
|
rval = QLA_SUCCESS;
|
|
fw->hccr = htons(RD_REG_WORD(®->hccr));
|
|
|
|
/* Pause RISC. */
|
|
WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
|
|
for (cnt = 30000; (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 &&
|
|
rval == QLA_SUCCESS; cnt--) {
|
|
if (cnt)
|
|
udelay(100);
|
|
else
|
|
rval = QLA_FUNCTION_TIMEOUT;
|
|
}
|
|
if (rval == QLA_SUCCESS) {
|
|
dmp_reg = ®->flash_address;
|
|
for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
|
|
fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
|
|
|
|
dmp_reg = ®->u.isp2100.mailbox0;
|
|
for (cnt = 0; cnt < ha->mbx_count; cnt++) {
|
|
if (cnt == 8)
|
|
dmp_reg = ®->u_end.isp2200.mailbox8;
|
|
|
|
fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
|
|
}
|
|
|
|
dmp_reg = ®->u.isp2100.unused_2[0];
|
|
for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
|
|
fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
|
|
|
|
WRT_REG_WORD(®->ctrl_status, 0x00);
|
|
dmp_reg = ®->risc_hw;
|
|
for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
|
|
fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
|
|
|
|
WRT_REG_WORD(®->pcr, 0x2000);
|
|
qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
|
|
|
|
WRT_REG_WORD(®->pcr, 0x2100);
|
|
qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
|
|
|
|
WRT_REG_WORD(®->pcr, 0x2200);
|
|
qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
|
|
|
|
WRT_REG_WORD(®->pcr, 0x2300);
|
|
qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
|
|
|
|
WRT_REG_WORD(®->pcr, 0x2400);
|
|
qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
|
|
|
|
WRT_REG_WORD(®->pcr, 0x2500);
|
|
qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
|
|
|
|
WRT_REG_WORD(®->pcr, 0x2600);
|
|
qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
|
|
|
|
WRT_REG_WORD(®->pcr, 0x2700);
|
|
qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
|
|
|
|
WRT_REG_WORD(®->ctrl_status, 0x10);
|
|
qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
|
|
|
|
WRT_REG_WORD(®->ctrl_status, 0x20);
|
|
qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
|
|
|
|
WRT_REG_WORD(®->ctrl_status, 0x30);
|
|
qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
|
|
|
|
/* Reset the ISP. */
|
|
WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET);
|
|
}
|
|
|
|
for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
|
|
rval == QLA_SUCCESS; cnt--) {
|
|
if (cnt)
|
|
udelay(100);
|
|
else
|
|
rval = QLA_FUNCTION_TIMEOUT;
|
|
}
|
|
|
|
/* Pause RISC. */
|
|
if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
|
|
(RD_REG_WORD(®->mctr) & (BIT_1 | BIT_0)) != 0))) {
|
|
|
|
WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
|
|
for (cnt = 30000;
|
|
(RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 &&
|
|
rval == QLA_SUCCESS; cnt--) {
|
|
if (cnt)
|
|
udelay(100);
|
|
else
|
|
rval = QLA_FUNCTION_TIMEOUT;
|
|
}
|
|
if (rval == QLA_SUCCESS) {
|
|
/* Set memory configuration and timing. */
|
|
if (IS_QLA2100(ha))
|
|
WRT_REG_WORD(®->mctr, 0xf1);
|
|
else
|
|
WRT_REG_WORD(®->mctr, 0xf2);
|
|
RD_REG_WORD(®->mctr); /* PCI Posting. */
|
|
|
|
/* Release RISC. */
|
|
WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC);
|
|
}
|
|
}
|
|
|
|
if (rval == QLA_SUCCESS) {
|
|
/* Get RISC SRAM. */
|
|
risc_address = 0x1000;
|
|
WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
|
|
clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
|
|
}
|
|
for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
|
|
cnt++, risc_address++) {
|
|
WRT_MAILBOX_REG(ha, reg, 1, risc_address);
|
|
WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT);
|
|
|
|
for (timer = 6000000; timer != 0; timer--) {
|
|
/* Check for pending interrupts. */
|
|
if (RD_REG_WORD(®->istatus) & ISR_RISC_INT) {
|
|
if (RD_REG_WORD(®->semaphore) & BIT_0) {
|
|
set_bit(MBX_INTERRUPT,
|
|
&ha->mbx_cmd_flags);
|
|
|
|
mb0 = RD_MAILBOX_REG(ha, reg, 0);
|
|
mb2 = RD_MAILBOX_REG(ha, reg, 2);
|
|
|
|
WRT_REG_WORD(®->semaphore, 0);
|
|
WRT_REG_WORD(®->hccr,
|
|
HCCR_CLR_RISC_INT);
|
|
RD_REG_WORD(®->hccr);
|
|
break;
|
|
}
|
|
WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
|
|
RD_REG_WORD(®->hccr);
|
|
}
|
|
udelay(5);
|
|
}
|
|
|
|
if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
|
|
rval = mb0 & MBS_MASK;
|
|
fw->risc_ram[cnt] = htons(mb2);
|
|
} else {
|
|
rval = QLA_FUNCTION_FAILED;
|
|
}
|
|
}
|
|
|
|
if (rval == QLA_SUCCESS)
|
|
qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
|
|
|
|
qla2xxx_dump_post_process(base_vha, rval);
|
|
|
|
qla2100_fw_dump_failed:
|
|
if (!hardware_locked)
|
|
spin_unlock_irqrestore(&ha->hardware_lock, flags);
|
|
}
|
|
|
|
void
|
|
qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
|
|
{
|
|
int rval;
|
|
uint32_t cnt;
|
|
uint32_t risc_address;
|
|
struct qla_hw_data *ha = vha->hw;
|
|
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
|
|
uint32_t __iomem *dmp_reg;
|
|
uint32_t *iter_reg;
|
|
uint16_t __iomem *mbx_reg;
|
|
unsigned long flags;
|
|
struct qla24xx_fw_dump *fw;
|
|
uint32_t ext_mem_cnt;
|
|
void *nxt;
|
|
struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
|
|
|
|
if (IS_QLA82XX(ha))
|
|
return;
|
|
|
|
risc_address = ext_mem_cnt = 0;
|
|
flags = 0;
|
|
|
|
if (!hardware_locked)
|
|
spin_lock_irqsave(&ha->hardware_lock, flags);
|
|
|
|
if (!ha->fw_dump) {
|
|
ql_log(ql_log_warn, vha, 0xd006,
|
|
"No buffer available for dump.\n");
|
|
goto qla24xx_fw_dump_failed;
|
|
}
|
|
|
|
if (ha->fw_dumped) {
|
|
ql_log(ql_log_warn, vha, 0xd007,
|
|
"Firmware has been previously dumped (%p) "
|
|
"-- ignoring request.\n",
|
|
ha->fw_dump);
|
|
goto qla24xx_fw_dump_failed;
|
|
}
|
|
fw = &ha->fw_dump->isp.isp24;
|
|
qla2xxx_prep_dump(ha, ha->fw_dump);
|
|
|
|
fw->host_status = htonl(RD_REG_DWORD(®->host_status));
|
|
|
|
/* Pause RISC. */
|
|
rval = qla24xx_pause_risc(reg);
|
|
if (rval != QLA_SUCCESS)
|
|
goto qla24xx_fw_dump_failed_0;
|
|
|
|
/* Host interface registers. */
|
|
dmp_reg = ®->flash_addr;
|
|
for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
|
|
fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
/* Disable interrupts. */
|
|
WRT_REG_DWORD(®->ictrl, 0);
|
|
RD_REG_DWORD(®->ictrl);
|
|
|
|
/* Shadow registers. */
|
|
WRT_REG_DWORD(®->iobase_addr, 0x0F70);
|
|
RD_REG_DWORD(®->iobase_addr);
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0000000);
|
|
fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0100000);
|
|
fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0200000);
|
|
fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0300000);
|
|
fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0400000);
|
|
fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0500000);
|
|
fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0600000);
|
|
fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
/* Mailbox registers. */
|
|
mbx_reg = ®->mailbox0;
|
|
for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
|
|
fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
|
|
|
|
/* Transfer sequence registers. */
|
|
iter_reg = fw->xseq_gp_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
|
|
|
|
qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
|
|
qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
|
|
|
|
/* Receive sequence registers. */
|
|
iter_reg = fw->rseq_gp_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
|
|
|
|
qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
|
|
qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
|
|
qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
|
|
|
|
/* Command DMA registers. */
|
|
qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
|
|
|
|
/* Queues. */
|
|
iter_reg = fw->req0_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
|
|
dmp_reg = ®->iobase_q;
|
|
for (cnt = 0; cnt < 7; cnt++)
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
iter_reg = fw->resp0_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
|
|
dmp_reg = ®->iobase_q;
|
|
for (cnt = 0; cnt < 7; cnt++)
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
iter_reg = fw->req1_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
|
|
dmp_reg = ®->iobase_q;
|
|
for (cnt = 0; cnt < 7; cnt++)
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
/* Transmit DMA registers. */
|
|
iter_reg = fw->xmt0_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x7610, 16, iter_reg);
|
|
|
|
iter_reg = fw->xmt1_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x7630, 16, iter_reg);
|
|
|
|
iter_reg = fw->xmt2_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x7650, 16, iter_reg);
|
|
|
|
iter_reg = fw->xmt3_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x7670, 16, iter_reg);
|
|
|
|
iter_reg = fw->xmt4_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x7690, 16, iter_reg);
|
|
|
|
qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
|
|
|
|
/* Receive DMA registers. */
|
|
iter_reg = fw->rcvt0_data_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x7710, 16, iter_reg);
|
|
|
|
iter_reg = fw->rcvt1_data_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x7730, 16, iter_reg);
|
|
|
|
/* RISC registers. */
|
|
iter_reg = fw->risc_gp_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
|
|
|
|
/* Local memory controller registers. */
|
|
iter_reg = fw->lmc_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x3060, 16, iter_reg);
|
|
|
|
/* Fibre Protocol Module registers. */
|
|
iter_reg = fw->fpm_hdw_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
|
|
|
|
/* Frame Buffer registers. */
|
|
iter_reg = fw->fb_hdw_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
|
|
|
|
rval = qla24xx_soft_reset(ha);
|
|
if (rval != QLA_SUCCESS)
|
|
goto qla24xx_fw_dump_failed_0;
|
|
|
|
rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
|
|
&nxt);
|
|
if (rval != QLA_SUCCESS)
|
|
goto qla24xx_fw_dump_failed_0;
|
|
|
|
nxt = qla2xxx_copy_queues(ha, nxt);
|
|
|
|
qla24xx_copy_eft(ha, nxt);
|
|
|
|
qla24xx_fw_dump_failed_0:
|
|
qla2xxx_dump_post_process(base_vha, rval);
|
|
|
|
qla24xx_fw_dump_failed:
|
|
if (!hardware_locked)
|
|
spin_unlock_irqrestore(&ha->hardware_lock, flags);
|
|
}
|
|
|
|
void
|
|
qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
|
|
{
|
|
int rval;
|
|
uint32_t cnt;
|
|
uint32_t risc_address;
|
|
struct qla_hw_data *ha = vha->hw;
|
|
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
|
|
uint32_t __iomem *dmp_reg;
|
|
uint32_t *iter_reg;
|
|
uint16_t __iomem *mbx_reg;
|
|
unsigned long flags;
|
|
struct qla25xx_fw_dump *fw;
|
|
uint32_t ext_mem_cnt;
|
|
void *nxt, *nxt_chain;
|
|
uint32_t *last_chain = NULL;
|
|
struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
|
|
|
|
risc_address = ext_mem_cnt = 0;
|
|
flags = 0;
|
|
|
|
if (!hardware_locked)
|
|
spin_lock_irqsave(&ha->hardware_lock, flags);
|
|
|
|
if (!ha->fw_dump) {
|
|
ql_log(ql_log_warn, vha, 0xd008,
|
|
"No buffer available for dump.\n");
|
|
goto qla25xx_fw_dump_failed;
|
|
}
|
|
|
|
if (ha->fw_dumped) {
|
|
ql_log(ql_log_warn, vha, 0xd009,
|
|
"Firmware has been previously dumped (%p) "
|
|
"-- ignoring request.\n",
|
|
ha->fw_dump);
|
|
goto qla25xx_fw_dump_failed;
|
|
}
|
|
fw = &ha->fw_dump->isp.isp25;
|
|
qla2xxx_prep_dump(ha, ha->fw_dump);
|
|
ha->fw_dump->version = __constant_htonl(2);
|
|
|
|
fw->host_status = htonl(RD_REG_DWORD(®->host_status));
|
|
|
|
/* Pause RISC. */
|
|
rval = qla24xx_pause_risc(reg);
|
|
if (rval != QLA_SUCCESS)
|
|
goto qla25xx_fw_dump_failed_0;
|
|
|
|
/* Host/Risc registers. */
|
|
iter_reg = fw->host_risc_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x7010, 16, iter_reg);
|
|
|
|
/* PCIe registers. */
|
|
WRT_REG_DWORD(®->iobase_addr, 0x7C00);
|
|
RD_REG_DWORD(®->iobase_addr);
|
|
WRT_REG_DWORD(®->iobase_window, 0x01);
|
|
dmp_reg = ®->iobase_c4;
|
|
fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
|
|
fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
|
|
fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
|
|
fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window));
|
|
|
|
WRT_REG_DWORD(®->iobase_window, 0x00);
|
|
RD_REG_DWORD(®->iobase_window);
|
|
|
|
/* Host interface registers. */
|
|
dmp_reg = ®->flash_addr;
|
|
for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
|
|
fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
/* Disable interrupts. */
|
|
WRT_REG_DWORD(®->ictrl, 0);
|
|
RD_REG_DWORD(®->ictrl);
|
|
|
|
/* Shadow registers. */
|
|
WRT_REG_DWORD(®->iobase_addr, 0x0F70);
|
|
RD_REG_DWORD(®->iobase_addr);
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0000000);
|
|
fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0100000);
|
|
fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0200000);
|
|
fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0300000);
|
|
fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0400000);
|
|
fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0500000);
|
|
fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0600000);
|
|
fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0700000);
|
|
fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0800000);
|
|
fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0900000);
|
|
fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0A00000);
|
|
fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
/* RISC I/O register. */
|
|
WRT_REG_DWORD(®->iobase_addr, 0x0010);
|
|
fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window));
|
|
|
|
/* Mailbox registers. */
|
|
mbx_reg = ®->mailbox0;
|
|
for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
|
|
fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
|
|
|
|
/* Transfer sequence registers. */
|
|
iter_reg = fw->xseq_gp_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
|
|
|
|
iter_reg = fw->xseq_0_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
|
|
|
|
qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
|
|
|
|
/* Receive sequence registers. */
|
|
iter_reg = fw->rseq_gp_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
|
|
|
|
iter_reg = fw->rseq_0_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
|
|
|
|
qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
|
|
qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
|
|
|
|
/* Auxiliary sequence registers. */
|
|
iter_reg = fw->aseq_gp_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0xB070, 16, iter_reg);
|
|
|
|
iter_reg = fw->aseq_0_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
|
|
|
|
qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
|
|
qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
|
|
|
|
/* Command DMA registers. */
|
|
qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
|
|
|
|
/* Queues. */
|
|
iter_reg = fw->req0_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
|
|
dmp_reg = ®->iobase_q;
|
|
for (cnt = 0; cnt < 7; cnt++)
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
iter_reg = fw->resp0_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
|
|
dmp_reg = ®->iobase_q;
|
|
for (cnt = 0; cnt < 7; cnt++)
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
iter_reg = fw->req1_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
|
|
dmp_reg = ®->iobase_q;
|
|
for (cnt = 0; cnt < 7; cnt++)
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
/* Transmit DMA registers. */
|
|
iter_reg = fw->xmt0_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x7610, 16, iter_reg);
|
|
|
|
iter_reg = fw->xmt1_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x7630, 16, iter_reg);
|
|
|
|
iter_reg = fw->xmt2_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x7650, 16, iter_reg);
|
|
|
|
iter_reg = fw->xmt3_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x7670, 16, iter_reg);
|
|
|
|
iter_reg = fw->xmt4_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x7690, 16, iter_reg);
|
|
|
|
qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
|
|
|
|
/* Receive DMA registers. */
|
|
iter_reg = fw->rcvt0_data_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x7710, 16, iter_reg);
|
|
|
|
iter_reg = fw->rcvt1_data_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x7730, 16, iter_reg);
|
|
|
|
/* RISC registers. */
|
|
iter_reg = fw->risc_gp_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
|
|
|
|
/* Local memory controller registers. */
|
|
iter_reg = fw->lmc_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x3070, 16, iter_reg);
|
|
|
|
/* Fibre Protocol Module registers. */
|
|
iter_reg = fw->fpm_hdw_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
|
|
|
|
/* Frame Buffer registers. */
|
|
iter_reg = fw->fb_hdw_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
|
|
|
|
/* Multi queue registers */
|
|
nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
|
|
&last_chain);
|
|
|
|
rval = qla24xx_soft_reset(ha);
|
|
if (rval != QLA_SUCCESS)
|
|
goto qla25xx_fw_dump_failed_0;
|
|
|
|
rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
|
|
&nxt);
|
|
if (rval != QLA_SUCCESS)
|
|
goto qla25xx_fw_dump_failed_0;
|
|
|
|
nxt = qla2xxx_copy_queues(ha, nxt);
|
|
|
|
nxt = qla24xx_copy_eft(ha, nxt);
|
|
|
|
/* Chain entries -- started with MQ. */
|
|
qla25xx_copy_fce(ha, nxt_chain, &last_chain);
|
|
if (last_chain) {
|
|
ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
|
|
*last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
|
|
}
|
|
|
|
qla25xx_fw_dump_failed_0:
|
|
qla2xxx_dump_post_process(base_vha, rval);
|
|
|
|
qla25xx_fw_dump_failed:
|
|
if (!hardware_locked)
|
|
spin_unlock_irqrestore(&ha->hardware_lock, flags);
|
|
}
|
|
|
|
void
|
|
qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
|
|
{
|
|
int rval;
|
|
uint32_t cnt;
|
|
uint32_t risc_address;
|
|
struct qla_hw_data *ha = vha->hw;
|
|
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
|
|
uint32_t __iomem *dmp_reg;
|
|
uint32_t *iter_reg;
|
|
uint16_t __iomem *mbx_reg;
|
|
unsigned long flags;
|
|
struct qla81xx_fw_dump *fw;
|
|
uint32_t ext_mem_cnt;
|
|
void *nxt, *nxt_chain;
|
|
uint32_t *last_chain = NULL;
|
|
struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
|
|
|
|
risc_address = ext_mem_cnt = 0;
|
|
flags = 0;
|
|
|
|
if (!hardware_locked)
|
|
spin_lock_irqsave(&ha->hardware_lock, flags);
|
|
|
|
if (!ha->fw_dump) {
|
|
ql_log(ql_log_warn, vha, 0xd00a,
|
|
"No buffer available for dump.\n");
|
|
goto qla81xx_fw_dump_failed;
|
|
}
|
|
|
|
if (ha->fw_dumped) {
|
|
ql_log(ql_log_warn, vha, 0xd00b,
|
|
"Firmware has been previously dumped (%p) "
|
|
"-- ignoring request.\n",
|
|
ha->fw_dump);
|
|
goto qla81xx_fw_dump_failed;
|
|
}
|
|
fw = &ha->fw_dump->isp.isp81;
|
|
qla2xxx_prep_dump(ha, ha->fw_dump);
|
|
|
|
fw->host_status = htonl(RD_REG_DWORD(®->host_status));
|
|
|
|
/* Pause RISC. */
|
|
rval = qla24xx_pause_risc(reg);
|
|
if (rval != QLA_SUCCESS)
|
|
goto qla81xx_fw_dump_failed_0;
|
|
|
|
/* Host/Risc registers. */
|
|
iter_reg = fw->host_risc_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x7010, 16, iter_reg);
|
|
|
|
/* PCIe registers. */
|
|
WRT_REG_DWORD(®->iobase_addr, 0x7C00);
|
|
RD_REG_DWORD(®->iobase_addr);
|
|
WRT_REG_DWORD(®->iobase_window, 0x01);
|
|
dmp_reg = ®->iobase_c4;
|
|
fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
|
|
fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
|
|
fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
|
|
fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window));
|
|
|
|
WRT_REG_DWORD(®->iobase_window, 0x00);
|
|
RD_REG_DWORD(®->iobase_window);
|
|
|
|
/* Host interface registers. */
|
|
dmp_reg = ®->flash_addr;
|
|
for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
|
|
fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
/* Disable interrupts. */
|
|
WRT_REG_DWORD(®->ictrl, 0);
|
|
RD_REG_DWORD(®->ictrl);
|
|
|
|
/* Shadow registers. */
|
|
WRT_REG_DWORD(®->iobase_addr, 0x0F70);
|
|
RD_REG_DWORD(®->iobase_addr);
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0000000);
|
|
fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0100000);
|
|
fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0200000);
|
|
fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0300000);
|
|
fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0400000);
|
|
fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0500000);
|
|
fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0600000);
|
|
fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0700000);
|
|
fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0800000);
|
|
fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0900000);
|
|
fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
WRT_REG_DWORD(®->iobase_select, 0xB0A00000);
|
|
fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata));
|
|
|
|
/* RISC I/O register. */
|
|
WRT_REG_DWORD(®->iobase_addr, 0x0010);
|
|
fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window));
|
|
|
|
/* Mailbox registers. */
|
|
mbx_reg = ®->mailbox0;
|
|
for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
|
|
fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
|
|
|
|
/* Transfer sequence registers. */
|
|
iter_reg = fw->xseq_gp_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
|
|
|
|
iter_reg = fw->xseq_0_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
|
|
|
|
qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
|
|
|
|
/* Receive sequence registers. */
|
|
iter_reg = fw->rseq_gp_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
|
|
|
|
iter_reg = fw->rseq_0_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
|
|
|
|
qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
|
|
qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
|
|
|
|
/* Auxiliary sequence registers. */
|
|
iter_reg = fw->aseq_gp_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0xB070, 16, iter_reg);
|
|
|
|
iter_reg = fw->aseq_0_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
|
|
|
|
qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
|
|
qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
|
|
|
|
/* Command DMA registers. */
|
|
qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
|
|
|
|
/* Queues. */
|
|
iter_reg = fw->req0_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
|
|
dmp_reg = ®->iobase_q;
|
|
for (cnt = 0; cnt < 7; cnt++)
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
iter_reg = fw->resp0_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
|
|
dmp_reg = ®->iobase_q;
|
|
for (cnt = 0; cnt < 7; cnt++)
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
iter_reg = fw->req1_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
|
|
dmp_reg = ®->iobase_q;
|
|
for (cnt = 0; cnt < 7; cnt++)
|
|
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
|
|
|
/* Transmit DMA registers. */
|
|
iter_reg = fw->xmt0_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x7610, 16, iter_reg);
|
|
|
|
iter_reg = fw->xmt1_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x7630, 16, iter_reg);
|
|
|
|
iter_reg = fw->xmt2_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x7650, 16, iter_reg);
|
|
|
|
iter_reg = fw->xmt3_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x7670, 16, iter_reg);
|
|
|
|
iter_reg = fw->xmt4_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x7690, 16, iter_reg);
|
|
|
|
qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
|
|
|
|
/* Receive DMA registers. */
|
|
iter_reg = fw->rcvt0_data_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x7710, 16, iter_reg);
|
|
|
|
iter_reg = fw->rcvt1_data_dma_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x7730, 16, iter_reg);
|
|
|
|
/* RISC registers. */
|
|
iter_reg = fw->risc_gp_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
|
|
|
|
/* Local memory controller registers. */
|
|
iter_reg = fw->lmc_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x3070, 16, iter_reg);
|
|
|
|
/* Fibre Protocol Module registers. */
|
|
iter_reg = fw->fpm_hdw_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
|
|
|
|
/* Frame Buffer registers. */
|
|
iter_reg = fw->fb_hdw_reg;
|
|
iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
|
|
iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
|
|
qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
|
|
|
|
/* Multi queue registers */
|
|
nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
|
|
&last_chain);
|
|
|
|
rval = qla24xx_soft_reset(ha);
|
|
if (rval != QLA_SUCCESS)
|
|
goto qla81xx_fw_dump_failed_0;
|
|
|
|
rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
|
|
&nxt);
|
|
if (rval != QLA_SUCCESS)
|
|
goto qla81xx_fw_dump_failed_0;
|
|
|
|
nxt = qla2xxx_copy_queues(ha, nxt);
|
|
|
|
nxt = qla24xx_copy_eft(ha, nxt);
|
|
|
|
/* Chain entries -- started with MQ. */
|
|
qla25xx_copy_fce(ha, nxt_chain, &last_chain);
|
|
if (last_chain) {
|
|
ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
|
|
*last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
|
|
}
|
|
|
|
qla81xx_fw_dump_failed_0:
|
|
qla2xxx_dump_post_process(base_vha, rval);
|
|
|
|
qla81xx_fw_dump_failed:
|
|
if (!hardware_locked)
|
|
spin_unlock_irqrestore(&ha->hardware_lock, flags);
|
|
}
|
|
|
|
/****************************************************************************/
|
|
/* Driver Debug Functions. */
|
|
/****************************************************************************/
|
|
/*
|
|
* This function is for formatting and logging debug information.
|
|
* It is to be used when vha is available. It formats the message
|
|
* and logs it to the messages file.
|
|
* parameters:
|
|
* level: The level of the debug messages to be printed.
|
|
* If ql2xextended_error_logging value is correctly set,
|
|
* this message will appear in the messages file.
|
|
* vha: Pointer to the scsi_qla_host_t.
|
|
* id: This is a unique identifier for the level. It identifies the
|
|
* part of the code from where the message originated.
|
|
* msg: The message to be displayed.
|
|
*/
|
|
void
|
|
ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, char *msg, ...) {
|
|
|
|
char pbuf[QL_DBG_BUF_LEN];
|
|
va_list ap;
|
|
uint32_t len;
|
|
struct pci_dev *pdev = NULL;
|
|
|
|
memset(pbuf, 0, QL_DBG_BUF_LEN);
|
|
|
|
va_start(ap, msg);
|
|
|
|
if ((level & ql2xextended_error_logging) == level) {
|
|
if (vha != NULL) {
|
|
pdev = vha->hw->pdev;
|
|
/* <module-name> <pci-name> <msg-id>:<host> Message */
|
|
sprintf(pbuf, "%s [%s]-%04x:%ld: ", QL_MSGHDR,
|
|
dev_name(&(pdev->dev)), id + ql_dbg_offset,
|
|
vha->host_no);
|
|
} else
|
|
sprintf(pbuf, "%s [%s]-%04x: : ", QL_MSGHDR,
|
|
"0000:00:00.0", id + ql_dbg_offset);
|
|
|
|
len = strlen(pbuf);
|
|
vsprintf(pbuf+len, msg, ap);
|
|
pr_warning("%s", pbuf);
|
|
}
|
|
|
|
va_end(ap);
|
|
|
|
}
|
|
|
|
/*
|
|
* This function is for formatting and logging debug information.
|
|
* It is to be used when vha is not available and pci is availble,
|
|
* i.e., before host allocation. It formats the message and logs it
|
|
* to the messages file.
|
|
* parameters:
|
|
* level: The level of the debug messages to be printed.
|
|
* If ql2xextended_error_logging value is correctly set,
|
|
* this message will appear in the messages file.
|
|
* pdev: Pointer to the struct pci_dev.
|
|
* id: This is a unique id for the level. It identifies the part
|
|
* of the code from where the message originated.
|
|
* msg: The message to be displayed.
|
|
*/
|
|
void
|
|
ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id, char *msg, ...) {
|
|
|
|
char pbuf[QL_DBG_BUF_LEN];
|
|
va_list ap;
|
|
uint32_t len;
|
|
|
|
if (pdev == NULL)
|
|
return;
|
|
|
|
memset(pbuf, 0, QL_DBG_BUF_LEN);
|
|
|
|
va_start(ap, msg);
|
|
|
|
if ((level & ql2xextended_error_logging) == level) {
|
|
/* <module-name> <dev-name>:<msg-id> Message */
|
|
sprintf(pbuf, "%s [%s]-%04x: : ", QL_MSGHDR,
|
|
dev_name(&(pdev->dev)), id + ql_dbg_offset);
|
|
|
|
len = strlen(pbuf);
|
|
vsprintf(pbuf+len, msg, ap);
|
|
pr_warning("%s", pbuf);
|
|
}
|
|
|
|
va_end(ap);
|
|
|
|
}
|
|
|
|
/*
|
|
* This function is for formatting and logging log messages.
|
|
* It is to be used when vha is available. It formats the message
|
|
* and logs it to the messages file. All the messages will be logged
|
|
* irrespective of value of ql2xextended_error_logging.
|
|
* parameters:
|
|
* level: The level of the log messages to be printed in the
|
|
* messages file.
|
|
* vha: Pointer to the scsi_qla_host_t
|
|
* id: This is a unique id for the level. It identifies the
|
|
* part of the code from where the message originated.
|
|
* msg: The message to be displayed.
|
|
*/
|
|
void
|
|
ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, char *msg, ...) {
|
|
|
|
char pbuf[QL_DBG_BUF_LEN];
|
|
va_list ap;
|
|
uint32_t len;
|
|
struct pci_dev *pdev = NULL;
|
|
|
|
memset(pbuf, 0, QL_DBG_BUF_LEN);
|
|
|
|
va_start(ap, msg);
|
|
|
|
if (level <= ql_errlev) {
|
|
if (vha != NULL) {
|
|
pdev = vha->hw->pdev;
|
|
/* <module-name> <msg-id>:<host> Message */
|
|
sprintf(pbuf, "%s [%s]-%04x:%ld: ", QL_MSGHDR,
|
|
dev_name(&(pdev->dev)), id, vha->host_no);
|
|
} else
|
|
sprintf(pbuf, "%s [%s]-%04x: : ", QL_MSGHDR,
|
|
"0000:00:00.0", id);
|
|
|
|
len = strlen(pbuf);
|
|
vsprintf(pbuf+len, msg, ap);
|
|
|
|
switch (level) {
|
|
case 0: /* FATAL LOG */
|
|
pr_crit("%s", pbuf);
|
|
break;
|
|
case 1:
|
|
pr_err("%s", pbuf);
|
|
break;
|
|
case 2:
|
|
pr_warn("%s", pbuf);
|
|
break;
|
|
default:
|
|
pr_info("%s", pbuf);
|
|
break;
|
|
}
|
|
}
|
|
|
|
va_end(ap);
|
|
}
|
|
|
|
/*
|
|
* This function is for formatting and logging log messages.
|
|
* It is to be used when vha is not available and pci is availble,
|
|
* i.e., before host allocation. It formats the message and logs
|
|
* it to the messages file. All the messages are logged irrespective
|
|
* of the value of ql2xextended_error_logging.
|
|
* parameters:
|
|
* level: The level of the log messages to be printed in the
|
|
* messages file.
|
|
* pdev: Pointer to the struct pci_dev.
|
|
* id: This is a unique id for the level. It identifies the
|
|
* part of the code from where the message originated.
|
|
* msg: The message to be displayed.
|
|
*/
|
|
void
|
|
ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id, char *msg, ...) {
|
|
|
|
char pbuf[QL_DBG_BUF_LEN];
|
|
va_list ap;
|
|
uint32_t len;
|
|
|
|
if (pdev == NULL)
|
|
return;
|
|
|
|
memset(pbuf, 0, QL_DBG_BUF_LEN);
|
|
|
|
va_start(ap, msg);
|
|
|
|
if (level <= ql_errlev) {
|
|
/* <module-name> <dev-name>:<msg-id> Message */
|
|
sprintf(pbuf, "%s [%s]-%04x: : ", QL_MSGHDR,
|
|
dev_name(&(pdev->dev)), id);
|
|
|
|
len = strlen(pbuf);
|
|
vsprintf(pbuf+len, msg, ap);
|
|
switch (level) {
|
|
case 0: /* FATAL LOG */
|
|
pr_crit("%s", pbuf);
|
|
break;
|
|
case 1:
|
|
pr_err("%s", pbuf);
|
|
break;
|
|
case 2:
|
|
pr_warn("%s", pbuf);
|
|
break;
|
|
default:
|
|
pr_info("%s", pbuf);
|
|
break;
|
|
}
|
|
}
|
|
|
|
va_end(ap);
|
|
}
|
|
|
|
void
|
|
ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
|
|
{
|
|
int i;
|
|
struct qla_hw_data *ha = vha->hw;
|
|
struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
|
|
struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
|
|
struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
|
|
uint16_t __iomem *mbx_reg;
|
|
|
|
if ((level & ql2xextended_error_logging) == level) {
|
|
|
|
if (IS_QLA82XX(ha))
|
|
mbx_reg = ®82->mailbox_in[0];
|
|
else if (IS_FWI2_CAPABLE(ha))
|
|
mbx_reg = ®24->mailbox0;
|
|
else
|
|
mbx_reg = MAILBOX_REG(ha, reg, 0);
|
|
|
|
ql_dbg(level, vha, id, "Mailbox registers:\n");
|
|
for (i = 0; i < 6; i++)
|
|
ql_dbg(level, vha, id,
|
|
"mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
|
|
}
|
|
}
|
|
|
|
|
|
void
|
|
ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
|
|
uint8_t *b, uint32_t size)
|
|
{
|
|
uint32_t cnt;
|
|
uint8_t c;
|
|
if ((level & ql2xextended_error_logging) == level) {
|
|
|
|
ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 "
|
|
"9 Ah Bh Ch Dh Eh Fh\n");
|
|
ql_dbg(level, vha, id, "----------------------------------"
|
|
"----------------------------\n");
|
|
|
|
ql_dbg(level, vha, id, "");
|
|
for (cnt = 0; cnt < size;) {
|
|
c = *b++;
|
|
printk("%02x", (uint32_t) c);
|
|
cnt++;
|
|
if (!(cnt % 16))
|
|
printk("\n");
|
|
else
|
|
printk(" ");
|
|
}
|
|
if (cnt % 16)
|
|
ql_dbg(level, vha, id, "\n");
|
|
}
|
|
}
|