forked from Minki/linux
b0db321ba1
The code in arch/arm/mach-prima2/headsmp.S is used for both boot time initialization and for cpu hotplug, so it must not be discarded after the initial boot is complete. This replaces the __INIT annotation with __CPUINIT, and marks the sirfsoc_cpu_die as __ref to annotate that it correctly uses the sections. Without this patch, building prima2_defconfig results in: WARNING: arch/arm/mach-prima2/built-in.o(.cpuinit.text+0x130): Section mismatch in reference from the function sirfsoc_boot_secondary() to the function .init.text:sirfsoc_secondary_startup() The function __cpuinit sirfsoc_boot_secondary() references a function __init sirfsoc_secondary_startup(). If sirfsoc_secondary_startup is only used by sirfsoc_boot_secondary then annotate sirfsoc_secondary_startup with a matching annotation. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Barry Song <baohua.song@csr.com>
81 lines
1.8 KiB
ArmAsm
81 lines
1.8 KiB
ArmAsm
/*
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* Entry of the second core for CSR Marco dual-core SMP SoCs
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*
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* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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__CPUINIT
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/*
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* Cold boot and hardware reset show different behaviour,
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* system will be always panic if we warm-reset the board
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* Here we invalidate L1 of CPU1 to make sure there isn't
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* uninitialized data written into memory later
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*/
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ENTRY(v7_invalidate_l1)
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 2, r0, c0, c0, 0
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mrc p15, 1, r0, c0, c0, 0
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ldr r1, =0x7fff
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and r2, r1, r0, lsr #13
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ldr r1, =0x3ff
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and r3, r1, r0, lsr #3 @ NumWays - 1
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add r2, r2, #1 @ NumSets
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and r0, r0, #0x7
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add r0, r0, #4 @ SetShift
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clz r1, r3 @ WayShift
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add r4, r3, #1 @ NumWays
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1: sub r2, r2, #1 @ NumSets--
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mov r3, r4 @ Temp = NumWays
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2: subs r3, r3, #1 @ Temp--
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mov r5, r3, lsl r1
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mov r6, r2, lsl r0
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orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
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mcr p15, 0, r5, c7, c6, 2
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bgt 2b
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cmp r2, #0
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bgt 1b
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dsb
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isb
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mov pc, lr
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ENDPROC(v7_invalidate_l1)
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/*
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* SIRFSOC specific entry point for secondary CPUs. This provides
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* a "holding pen" into which all secondary cores are held until we're
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* ready for them to initialise.
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*/
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ENTRY(sirfsoc_secondary_startup)
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bl v7_invalidate_l1
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mrc p15, 0, r0, c0, c0, 5
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and r0, r0, #15
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adr r4, 1f
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ldmia r4, {r5, r6}
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sub r4, r4, r5
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add r6, r6, r4
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pen: ldr r7, [r6]
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cmp r7, r0
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bne pen
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/*
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* we've been released from the holding pen: secondary_stack
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* should now contain the SVC stack for this core
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*/
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b secondary_startup
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ENDPROC(sirfsoc_secondary_startup)
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.align
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1: .long .
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.long pen_release
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