forked from Minki/linux
a8f064c602
Get the switch id and save it away in the private mv88x6xxx structure in a centralised piece of code, rather than each driver doing it itself. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: David S. Miller <davem@davemloft.net>
1199 lines
26 KiB
C
1199 lines
26 KiB
C
/*
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* net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
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* Copyright (c) 2008 Marvell Semiconductor
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/delay.h>
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#include <linux/etherdevice.h>
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#include <linux/if_bridge.h>
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#include <linux/jiffies.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/phy.h>
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#include <net/dsa.h>
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#include "mv88e6xxx.h"
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/* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
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* use all 32 SMI bus addresses on its SMI bus, and all switch registers
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* will be directly accessible on some {device address,register address}
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* pair. If the ADDR[4:0] pins are not strapped to zero, the switch
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* will only respond to SMI transactions to that specific address, and
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* an indirect addressing mechanism needs to be used to access its
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* registers.
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*/
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static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
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{
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int ret;
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int i;
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for (i = 0; i < 16; i++) {
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ret = mdiobus_read(bus, sw_addr, 0);
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if (ret < 0)
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return ret;
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if ((ret & 0x8000) == 0)
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return 0;
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}
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return -ETIMEDOUT;
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}
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int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg)
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{
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int ret;
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if (sw_addr == 0)
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return mdiobus_read(bus, addr, reg);
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/* Wait for the bus to become free. */
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ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
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if (ret < 0)
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return ret;
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/* Transmit the read command. */
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ret = mdiobus_write(bus, sw_addr, 0, 0x9800 | (addr << 5) | reg);
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if (ret < 0)
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return ret;
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/* Wait for the read command to complete. */
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ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
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if (ret < 0)
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return ret;
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/* Read the data. */
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ret = mdiobus_read(bus, sw_addr, 1);
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if (ret < 0)
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return ret;
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return ret & 0xffff;
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}
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/* Must be called with SMI mutex held */
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static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
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{
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struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
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int ret;
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if (bus == NULL)
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return -EINVAL;
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ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
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if (ret < 0)
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return ret;
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dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
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addr, reg, ret);
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return ret;
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}
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int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
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{
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struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
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int ret;
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mutex_lock(&ps->smi_mutex);
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ret = _mv88e6xxx_reg_read(ds, addr, reg);
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mutex_unlock(&ps->smi_mutex);
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return ret;
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}
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int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
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int reg, u16 val)
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{
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int ret;
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if (sw_addr == 0)
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return mdiobus_write(bus, addr, reg, val);
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/* Wait for the bus to become free. */
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ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
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if (ret < 0)
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return ret;
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/* Transmit the data to write. */
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ret = mdiobus_write(bus, sw_addr, 1, val);
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if (ret < 0)
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return ret;
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/* Transmit the write command. */
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ret = mdiobus_write(bus, sw_addr, 0, 0x9400 | (addr << 5) | reg);
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if (ret < 0)
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return ret;
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/* Wait for the write command to complete. */
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ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
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if (ret < 0)
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return ret;
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return 0;
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}
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/* Must be called with SMI mutex held */
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static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
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u16 val)
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{
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struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
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if (bus == NULL)
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return -EINVAL;
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dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
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addr, reg, val);
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return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
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}
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int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
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{
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struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
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int ret;
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mutex_lock(&ps->smi_mutex);
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ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
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mutex_unlock(&ps->smi_mutex);
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return ret;
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}
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int mv88e6xxx_config_prio(struct dsa_switch *ds)
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{
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/* Configure the IP ToS mapping registers. */
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REG_WRITE(REG_GLOBAL, 0x10, 0x0000);
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REG_WRITE(REG_GLOBAL, 0x11, 0x0000);
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REG_WRITE(REG_GLOBAL, 0x12, 0x5555);
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REG_WRITE(REG_GLOBAL, 0x13, 0x5555);
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REG_WRITE(REG_GLOBAL, 0x14, 0xaaaa);
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REG_WRITE(REG_GLOBAL, 0x15, 0xaaaa);
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REG_WRITE(REG_GLOBAL, 0x16, 0xffff);
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REG_WRITE(REG_GLOBAL, 0x17, 0xffff);
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/* Configure the IEEE 802.1p priority mapping register. */
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REG_WRITE(REG_GLOBAL, 0x18, 0xfa41);
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return 0;
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}
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int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
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{
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REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
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REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
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REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);
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return 0;
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}
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int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
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{
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int i;
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int ret;
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for (i = 0; i < 6; i++) {
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int j;
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/* Write the MAC address byte. */
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REG_WRITE(REG_GLOBAL2, 0x0d, 0x8000 | (i << 8) | addr[i]);
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/* Wait for the write to complete. */
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for (j = 0; j < 16; j++) {
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ret = REG_READ(REG_GLOBAL2, 0x0d);
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if ((ret & 0x8000) == 0)
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break;
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}
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if (j == 16)
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return -ETIMEDOUT;
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}
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return 0;
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}
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int mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
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{
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if (addr >= 0)
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return mv88e6xxx_reg_read(ds, addr, regnum);
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return 0xffff;
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}
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int mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum, u16 val)
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{
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if (addr >= 0)
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return mv88e6xxx_reg_write(ds, addr, regnum, val);
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return 0;
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}
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#ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
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static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
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{
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int ret;
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unsigned long timeout;
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ret = REG_READ(REG_GLOBAL, 0x04);
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REG_WRITE(REG_GLOBAL, 0x04, ret & ~0x4000);
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timeout = jiffies + 1 * HZ;
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while (time_before(jiffies, timeout)) {
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ret = REG_READ(REG_GLOBAL, 0x00);
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usleep_range(1000, 2000);
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if ((ret & 0xc000) != 0xc000)
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return 0;
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}
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return -ETIMEDOUT;
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}
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static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
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{
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int ret;
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unsigned long timeout;
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ret = REG_READ(REG_GLOBAL, 0x04);
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REG_WRITE(REG_GLOBAL, 0x04, ret | 0x4000);
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timeout = jiffies + 1 * HZ;
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while (time_before(jiffies, timeout)) {
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ret = REG_READ(REG_GLOBAL, 0x00);
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usleep_range(1000, 2000);
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if ((ret & 0xc000) == 0xc000)
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return 0;
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}
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return -ETIMEDOUT;
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}
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static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
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{
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struct mv88e6xxx_priv_state *ps;
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ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
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if (mutex_trylock(&ps->ppu_mutex)) {
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struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
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if (mv88e6xxx_ppu_enable(ds) == 0)
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ps->ppu_disabled = 0;
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mutex_unlock(&ps->ppu_mutex);
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}
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}
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static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
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{
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struct mv88e6xxx_priv_state *ps = (void *)_ps;
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schedule_work(&ps->ppu_work);
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}
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static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
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{
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struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
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int ret;
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mutex_lock(&ps->ppu_mutex);
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/* If the PHY polling unit is enabled, disable it so that
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* we can access the PHY registers. If it was already
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* disabled, cancel the timer that is going to re-enable
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* it.
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*/
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if (!ps->ppu_disabled) {
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ret = mv88e6xxx_ppu_disable(ds);
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if (ret < 0) {
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mutex_unlock(&ps->ppu_mutex);
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return ret;
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}
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ps->ppu_disabled = 1;
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} else {
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del_timer(&ps->ppu_timer);
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ret = 0;
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}
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return ret;
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}
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static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
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{
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struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
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/* Schedule a timer to re-enable the PHY polling unit. */
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mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
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mutex_unlock(&ps->ppu_mutex);
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}
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void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
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{
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struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
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mutex_init(&ps->ppu_mutex);
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INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
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init_timer(&ps->ppu_timer);
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ps->ppu_timer.data = (unsigned long)ps;
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ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
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}
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int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
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{
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int ret;
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ret = mv88e6xxx_ppu_access_get(ds);
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if (ret >= 0) {
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ret = mv88e6xxx_reg_read(ds, addr, regnum);
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mv88e6xxx_ppu_access_put(ds);
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}
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return ret;
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}
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int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
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int regnum, u16 val)
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{
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int ret;
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ret = mv88e6xxx_ppu_access_get(ds);
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if (ret >= 0) {
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ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
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mv88e6xxx_ppu_access_put(ds);
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}
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return ret;
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}
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#endif
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void mv88e6xxx_poll_link(struct dsa_switch *ds)
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{
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int i;
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for (i = 0; i < DSA_MAX_PORTS; i++) {
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struct net_device *dev;
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int uninitialized_var(port_status);
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int link;
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int speed;
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int duplex;
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int fc;
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dev = ds->ports[i];
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if (dev == NULL)
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continue;
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link = 0;
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if (dev->flags & IFF_UP) {
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port_status = mv88e6xxx_reg_read(ds, REG_PORT(i), 0x00);
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if (port_status < 0)
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continue;
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link = !!(port_status & 0x0800);
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}
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if (!link) {
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if (netif_carrier_ok(dev)) {
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netdev_info(dev, "link down\n");
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netif_carrier_off(dev);
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}
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continue;
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}
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switch (port_status & 0x0300) {
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case 0x0000:
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speed = 10;
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break;
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case 0x0100:
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speed = 100;
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break;
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case 0x0200:
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speed = 1000;
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break;
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default:
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speed = -1;
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break;
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}
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duplex = (port_status & 0x0400) ? 1 : 0;
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fc = (port_status & 0x8000) ? 1 : 0;
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if (!netif_carrier_ok(dev)) {
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netdev_info(dev,
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"link up, %d Mb/s, %s duplex, flow control %sabled\n",
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speed,
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duplex ? "full" : "half",
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fc ? "en" : "dis");
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netif_carrier_on(dev);
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}
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}
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}
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static int mv88e6xxx_stats_wait(struct dsa_switch *ds)
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{
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int ret;
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int i;
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for (i = 0; i < 10; i++) {
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ret = REG_READ(REG_GLOBAL, 0x1d);
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if ((ret & 0x8000) == 0)
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return 0;
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}
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return -ETIMEDOUT;
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}
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static int mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
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{
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int ret;
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/* Snapshot the hardware statistics counters for this port. */
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REG_WRITE(REG_GLOBAL, 0x1d, 0xdc00 | port);
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/* Wait for the snapshotting to complete. */
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ret = mv88e6xxx_stats_wait(ds);
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if (ret < 0)
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return ret;
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return 0;
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}
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static void mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
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{
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u32 _val;
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int ret;
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*val = 0;
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ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x1d, 0xcc00 | stat);
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if (ret < 0)
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return;
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ret = mv88e6xxx_stats_wait(ds);
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if (ret < 0)
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return;
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ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1e);
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if (ret < 0)
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return;
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_val = ret << 16;
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ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1f);
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if (ret < 0)
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return;
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*val = _val | ret;
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}
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void mv88e6xxx_get_strings(struct dsa_switch *ds,
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int nr_stats, struct mv88e6xxx_hw_stat *stats,
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int port, uint8_t *data)
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{
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int i;
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for (i = 0; i < nr_stats; i++) {
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memcpy(data + i * ETH_GSTRING_LEN,
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stats[i].string, ETH_GSTRING_LEN);
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}
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}
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void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
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int nr_stats, struct mv88e6xxx_hw_stat *stats,
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int port, uint64_t *data)
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{
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struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
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int ret;
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int i;
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mutex_lock(&ps->stats_mutex);
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ret = mv88e6xxx_stats_snapshot(ds, port);
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if (ret < 0) {
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mutex_unlock(&ps->stats_mutex);
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return;
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}
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/* Read each of the counters. */
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for (i = 0; i < nr_stats; i++) {
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struct mv88e6xxx_hw_stat *s = stats + i;
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u32 low;
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u32 high = 0;
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if (s->reg >= 0x100) {
|
|
int ret;
|
|
|
|
ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
|
|
s->reg - 0x100);
|
|
if (ret < 0)
|
|
goto error;
|
|
low = ret;
|
|
if (s->sizeof_stat == 4) {
|
|
ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
|
|
s->reg - 0x100 + 1);
|
|
if (ret < 0)
|
|
goto error;
|
|
high = ret;
|
|
}
|
|
data[i] = (((u64)high) << 16) | low;
|
|
continue;
|
|
}
|
|
mv88e6xxx_stats_read(ds, s->reg, &low);
|
|
if (s->sizeof_stat == 8)
|
|
mv88e6xxx_stats_read(ds, s->reg + 1, &high);
|
|
|
|
data[i] = (((u64)high) << 32) | low;
|
|
}
|
|
error:
|
|
mutex_unlock(&ps->stats_mutex);
|
|
}
|
|
|
|
int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
|
|
{
|
|
return 32 * sizeof(u16);
|
|
}
|
|
|
|
void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
|
|
struct ethtool_regs *regs, void *_p)
|
|
{
|
|
u16 *p = _p;
|
|
int i;
|
|
|
|
regs->version = 0;
|
|
|
|
memset(p, 0xff, 32 * sizeof(u16));
|
|
|
|
for (i = 0; i < 32; i++) {
|
|
int ret;
|
|
|
|
ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
|
|
if (ret >= 0)
|
|
p[i] = ret;
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_NET_DSA_HWMON
|
|
|
|
int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
|
|
{
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
int ret;
|
|
int val;
|
|
|
|
*temp = 0;
|
|
|
|
mutex_lock(&ps->phy_mutex);
|
|
|
|
ret = mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
|
|
if (ret < 0)
|
|
goto error;
|
|
|
|
/* Enable temperature sensor */
|
|
ret = mv88e6xxx_phy_read(ds, 0x0, 0x1a);
|
|
if (ret < 0)
|
|
goto error;
|
|
|
|
ret = mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
|
|
if (ret < 0)
|
|
goto error;
|
|
|
|
/* Wait for temperature to stabilize */
|
|
usleep_range(10000, 12000);
|
|
|
|
val = mv88e6xxx_phy_read(ds, 0x0, 0x1a);
|
|
if (val < 0) {
|
|
ret = val;
|
|
goto error;
|
|
}
|
|
|
|
/* Disable temperature sensor */
|
|
ret = mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
|
|
if (ret < 0)
|
|
goto error;
|
|
|
|
*temp = ((val & 0x1f) - 5) * 5;
|
|
|
|
error:
|
|
mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
|
|
mutex_unlock(&ps->phy_mutex);
|
|
return ret;
|
|
}
|
|
#endif /* CONFIG_NET_DSA_HWMON */
|
|
|
|
static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
|
|
{
|
|
unsigned long timeout = jiffies + HZ / 10;
|
|
|
|
while (time_before(jiffies, timeout)) {
|
|
int ret;
|
|
|
|
ret = REG_READ(reg, offset);
|
|
if (!(ret & mask))
|
|
return 0;
|
|
|
|
usleep_range(1000, 2000);
|
|
}
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
int mv88e6xxx_phy_wait(struct dsa_switch *ds)
|
|
{
|
|
return mv88e6xxx_wait(ds, REG_GLOBAL2, 0x18, 0x8000);
|
|
}
|
|
|
|
int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
|
|
{
|
|
return mv88e6xxx_wait(ds, REG_GLOBAL2, 0x14, 0x0800);
|
|
}
|
|
|
|
int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
|
|
{
|
|
return mv88e6xxx_wait(ds, REG_GLOBAL2, 0x14, 0x8000);
|
|
}
|
|
|
|
/* Must be called with SMI lock held */
|
|
static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
|
|
{
|
|
unsigned long timeout = jiffies + HZ / 10;
|
|
|
|
while (time_before(jiffies, timeout)) {
|
|
int ret;
|
|
|
|
ret = _mv88e6xxx_reg_read(ds, reg, offset);
|
|
if (ret < 0)
|
|
return ret;
|
|
if (!(ret & mask))
|
|
return 0;
|
|
|
|
usleep_range(1000, 2000);
|
|
}
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
/* Must be called with SMI lock held */
|
|
static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
|
|
{
|
|
return _mv88e6xxx_wait(ds, REG_GLOBAL, 0x0b, ATU_BUSY);
|
|
}
|
|
|
|
int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, int regnum)
|
|
{
|
|
int ret;
|
|
|
|
REG_WRITE(REG_GLOBAL2, 0x18, 0x9800 | (addr << 5) | regnum);
|
|
|
|
ret = mv88e6xxx_phy_wait(ds);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
return REG_READ(REG_GLOBAL2, 0x19);
|
|
}
|
|
|
|
int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, int regnum,
|
|
u16 val)
|
|
{
|
|
REG_WRITE(REG_GLOBAL2, 0x19, val);
|
|
REG_WRITE(REG_GLOBAL2, 0x18, 0x9400 | (addr << 5) | regnum);
|
|
|
|
return mv88e6xxx_phy_wait(ds);
|
|
}
|
|
|
|
int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
|
|
{
|
|
int reg;
|
|
|
|
reg = mv88e6xxx_phy_read_indirect(ds, port, 16);
|
|
if (reg < 0)
|
|
return -EOPNOTSUPP;
|
|
|
|
e->eee_enabled = !!(reg & 0x0200);
|
|
e->tx_lpi_enabled = !!(reg & 0x0100);
|
|
|
|
reg = REG_READ(REG_PORT(port), 0);
|
|
e->eee_active = !!(reg & 0x0040);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mv88e6xxx_eee_enable_set(struct dsa_switch *ds, int port,
|
|
bool eee_enabled, bool tx_lpi_enabled)
|
|
{
|
|
int reg, nreg;
|
|
|
|
reg = mv88e6xxx_phy_read_indirect(ds, port, 16);
|
|
if (reg < 0)
|
|
return reg;
|
|
|
|
nreg = reg & ~0x0300;
|
|
if (eee_enabled)
|
|
nreg |= 0x0200;
|
|
if (tx_lpi_enabled)
|
|
nreg |= 0x0100;
|
|
|
|
if (nreg != reg)
|
|
return mv88e6xxx_phy_write_indirect(ds, port, 16, nreg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
|
|
struct phy_device *phydev, struct ethtool_eee *e)
|
|
{
|
|
int ret;
|
|
|
|
ret = mv88e6xxx_eee_enable_set(ds, port, e->eee_enabled,
|
|
e->tx_lpi_enabled);
|
|
if (ret)
|
|
return -EOPNOTSUPP;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, int fid, u16 cmd)
|
|
{
|
|
int ret;
|
|
|
|
ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x01, fid);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x0b, cmd);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
return _mv88e6xxx_atu_wait(ds);
|
|
}
|
|
|
|
static int _mv88e6xxx_flush_fid(struct dsa_switch *ds, int fid)
|
|
{
|
|
int ret;
|
|
|
|
ret = _mv88e6xxx_atu_wait(ds);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
return _mv88e6xxx_atu_cmd(ds, fid, ATU_CMD_FLUSH_NONSTATIC_FID);
|
|
}
|
|
|
|
static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state)
|
|
{
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
int reg, ret;
|
|
u8 oldstate;
|
|
|
|
mutex_lock(&ps->smi_mutex);
|
|
|
|
reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), 0x04);
|
|
if (reg < 0)
|
|
goto abort;
|
|
|
|
oldstate = reg & PSTATE_MASK;
|
|
if (oldstate != state) {
|
|
/* Flush forwarding database if we're moving a port
|
|
* from Learning or Forwarding state to Disabled or
|
|
* Blocking or Listening state.
|
|
*/
|
|
if (oldstate >= PSTATE_LEARNING && state <= PSTATE_BLOCKING) {
|
|
ret = _mv88e6xxx_flush_fid(ds, ps->fid[port]);
|
|
if (ret)
|
|
goto abort;
|
|
}
|
|
reg = (reg & ~PSTATE_MASK) | state;
|
|
ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x04, reg);
|
|
}
|
|
|
|
abort:
|
|
mutex_unlock(&ps->smi_mutex);
|
|
return ret;
|
|
}
|
|
|
|
/* Must be called with smi lock held */
|
|
static int _mv88e6xxx_update_port_config(struct dsa_switch *ds, int port)
|
|
{
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
u8 fid = ps->fid[port];
|
|
u16 reg = fid << 12;
|
|
|
|
if (dsa_is_cpu_port(ds, port))
|
|
reg |= ds->phys_port_mask;
|
|
else
|
|
reg |= (ps->bridge_mask[fid] |
|
|
(1 << dsa_upstream_port(ds))) & ~(1 << port);
|
|
|
|
return _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x06, reg);
|
|
}
|
|
|
|
/* Must be called with smi lock held */
|
|
static int _mv88e6xxx_update_bridge_config(struct dsa_switch *ds, int fid)
|
|
{
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
int port;
|
|
u32 mask;
|
|
int ret;
|
|
|
|
mask = ds->phys_port_mask;
|
|
while (mask) {
|
|
port = __ffs(mask);
|
|
mask &= ~(1 << port);
|
|
if (ps->fid[port] != fid)
|
|
continue;
|
|
|
|
ret = _mv88e6xxx_update_port_config(ds, port);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return _mv88e6xxx_flush_fid(ds, fid);
|
|
}
|
|
|
|
/* Bridge handling functions */
|
|
|
|
int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
|
|
{
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
int ret = 0;
|
|
u32 nmask;
|
|
int fid;
|
|
|
|
/* If the bridge group is not empty, join that group.
|
|
* Otherwise create a new group.
|
|
*/
|
|
fid = ps->fid[port];
|
|
nmask = br_port_mask & ~(1 << port);
|
|
if (nmask)
|
|
fid = ps->fid[__ffs(nmask)];
|
|
|
|
nmask = ps->bridge_mask[fid] | (1 << port);
|
|
if (nmask != br_port_mask) {
|
|
netdev_err(ds->ports[port],
|
|
"join: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
|
|
fid, br_port_mask, nmask);
|
|
return -EINVAL;
|
|
}
|
|
|
|
mutex_lock(&ps->smi_mutex);
|
|
|
|
ps->bridge_mask[fid] = br_port_mask;
|
|
|
|
if (fid != ps->fid[port]) {
|
|
ps->fid_mask |= 1 << ps->fid[port];
|
|
ps->fid[port] = fid;
|
|
ret = _mv88e6xxx_update_bridge_config(ds, fid);
|
|
}
|
|
|
|
mutex_unlock(&ps->smi_mutex);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
|
|
{
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
u8 fid, newfid;
|
|
int ret;
|
|
|
|
fid = ps->fid[port];
|
|
|
|
if (ps->bridge_mask[fid] != br_port_mask) {
|
|
netdev_err(ds->ports[port],
|
|
"leave: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
|
|
fid, br_port_mask, ps->bridge_mask[fid]);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* If the port was the last port of a bridge, we are done.
|
|
* Otherwise assign a new fid to the port, and fix up
|
|
* the bridge configuration.
|
|
*/
|
|
if (br_port_mask == (1 << port))
|
|
return 0;
|
|
|
|
mutex_lock(&ps->smi_mutex);
|
|
|
|
newfid = __ffs(ps->fid_mask);
|
|
ps->fid[port] = newfid;
|
|
ps->fid_mask &= (1 << newfid);
|
|
ps->bridge_mask[fid] &= ~(1 << port);
|
|
ps->bridge_mask[newfid] = 1 << port;
|
|
|
|
ret = _mv88e6xxx_update_bridge_config(ds, fid);
|
|
if (!ret)
|
|
ret = _mv88e6xxx_update_bridge_config(ds, newfid);
|
|
|
|
mutex_unlock(&ps->smi_mutex);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
|
|
{
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
int stp_state;
|
|
|
|
switch (state) {
|
|
case BR_STATE_DISABLED:
|
|
stp_state = PSTATE_DISABLED;
|
|
break;
|
|
case BR_STATE_BLOCKING:
|
|
case BR_STATE_LISTENING:
|
|
stp_state = PSTATE_BLOCKING;
|
|
break;
|
|
case BR_STATE_LEARNING:
|
|
stp_state = PSTATE_LEARNING;
|
|
break;
|
|
case BR_STATE_FORWARDING:
|
|
default:
|
|
stp_state = PSTATE_FORWARDING;
|
|
break;
|
|
}
|
|
|
|
netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state);
|
|
|
|
/* mv88e6xxx_port_stp_update may be called with softirqs disabled,
|
|
* so we can not update the port state directly but need to schedule it.
|
|
*/
|
|
ps->port_state[port] = stp_state;
|
|
set_bit(port, &ps->port_state_update_mask);
|
|
schedule_work(&ps->bridge_work);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __mv88e6xxx_write_addr(struct dsa_switch *ds,
|
|
const unsigned char *addr)
|
|
{
|
|
int i, ret;
|
|
|
|
for (i = 0; i < 3; i++) {
|
|
ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x0d + i,
|
|
(addr[i * 2] << 8) | addr[i * 2 + 1]);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __mv88e6xxx_read_addr(struct dsa_switch *ds, unsigned char *addr)
|
|
{
|
|
int i, ret;
|
|
|
|
for (i = 0; i < 3; i++) {
|
|
ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x0d + i);
|
|
if (ret < 0)
|
|
return ret;
|
|
addr[i * 2] = ret >> 8;
|
|
addr[i * 2 + 1] = ret & 0xff;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __mv88e6xxx_port_fdb_cmd(struct dsa_switch *ds, int port,
|
|
const unsigned char *addr, int state)
|
|
{
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
u8 fid = ps->fid[port];
|
|
int ret;
|
|
|
|
ret = _mv88e6xxx_atu_wait(ds);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = __mv88e6xxx_write_addr(ds, addr);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x0c,
|
|
(0x10 << port) | state);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = _mv88e6xxx_atu_cmd(ds, fid, ATU_CMD_LOAD_FID);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
|
|
const unsigned char *addr, u16 vid)
|
|
{
|
|
int state = is_multicast_ether_addr(addr) ?
|
|
FDB_STATE_MC_STATIC : FDB_STATE_STATIC;
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
int ret;
|
|
|
|
mutex_lock(&ps->smi_mutex);
|
|
ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr, state);
|
|
mutex_unlock(&ps->smi_mutex);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
|
|
const unsigned char *addr, u16 vid)
|
|
{
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
int ret;
|
|
|
|
mutex_lock(&ps->smi_mutex);
|
|
ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr, FDB_STATE_UNUSED);
|
|
mutex_unlock(&ps->smi_mutex);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int __mv88e6xxx_port_getnext(struct dsa_switch *ds, int port,
|
|
unsigned char *addr, bool *is_static)
|
|
{
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
u8 fid = ps->fid[port];
|
|
int ret, state;
|
|
|
|
ret = _mv88e6xxx_atu_wait(ds);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = __mv88e6xxx_write_addr(ds, addr);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
do {
|
|
ret = _mv88e6xxx_atu_cmd(ds, fid, ATU_CMD_GETNEXT_FID);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x0c);
|
|
if (ret < 0)
|
|
return ret;
|
|
state = ret & FDB_STATE_MASK;
|
|
if (state == FDB_STATE_UNUSED)
|
|
return -ENOENT;
|
|
} while (!(((ret >> 4) & 0xff) & (1 << port)));
|
|
|
|
ret = __mv88e6xxx_read_addr(ds, addr);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
*is_static = state == (is_multicast_ether_addr(addr) ?
|
|
FDB_STATE_MC_STATIC : FDB_STATE_STATIC);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* get next entry for port */
|
|
int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port,
|
|
unsigned char *addr, bool *is_static)
|
|
{
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
int ret;
|
|
|
|
mutex_lock(&ps->smi_mutex);
|
|
ret = __mv88e6xxx_port_getnext(ds, port, addr, is_static);
|
|
mutex_unlock(&ps->smi_mutex);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void mv88e6xxx_bridge_work(struct work_struct *work)
|
|
{
|
|
struct mv88e6xxx_priv_state *ps;
|
|
struct dsa_switch *ds;
|
|
int port;
|
|
|
|
ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
|
|
ds = ((struct dsa_switch *)ps) - 1;
|
|
|
|
while (ps->port_state_update_mask) {
|
|
port = __ffs(ps->port_state_update_mask);
|
|
clear_bit(port, &ps->port_state_update_mask);
|
|
mv88e6xxx_set_port_state(ds, port, ps->port_state[port]);
|
|
}
|
|
}
|
|
|
|
int mv88e6xxx_setup_port_common(struct dsa_switch *ds, int port)
|
|
{
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
int ret, fid;
|
|
|
|
mutex_lock(&ps->smi_mutex);
|
|
|
|
/* Port Control 1: disable trunking, disable sending
|
|
* learning messages to this port.
|
|
*/
|
|
ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x05, 0x0000);
|
|
if (ret)
|
|
goto abort;
|
|
|
|
/* Port based VLAN map: give each port its own address
|
|
* database, allow the CPU port to talk to each of the 'real'
|
|
* ports, and allow each of the 'real' ports to only talk to
|
|
* the upstream port.
|
|
*/
|
|
fid = __ffs(ps->fid_mask);
|
|
ps->fid[port] = fid;
|
|
ps->fid_mask &= ~(1 << fid);
|
|
|
|
if (!dsa_is_cpu_port(ds, port))
|
|
ps->bridge_mask[fid] = 1 << port;
|
|
|
|
ret = _mv88e6xxx_update_port_config(ds, port);
|
|
if (ret)
|
|
goto abort;
|
|
|
|
/* Default VLAN ID and priority: don't set a default VLAN
|
|
* ID, and set the default packet priority to zero.
|
|
*/
|
|
ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x07, 0x0000);
|
|
abort:
|
|
mutex_unlock(&ps->smi_mutex);
|
|
return ret;
|
|
}
|
|
|
|
int mv88e6xxx_setup_common(struct dsa_switch *ds)
|
|
{
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
|
|
mutex_init(&ps->smi_mutex);
|
|
mutex_init(&ps->stats_mutex);
|
|
mutex_init(&ps->phy_mutex);
|
|
|
|
ps->id = REG_READ(REG_PORT(0), 0x03) & 0xfff0;
|
|
|
|
ps->fid_mask = (1 << DSA_MAX_PORTS) - 1;
|
|
|
|
INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __init mv88e6xxx_init(void)
|
|
{
|
|
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
|
|
register_switch_driver(&mv88e6131_switch_driver);
|
|
#endif
|
|
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
|
|
register_switch_driver(&mv88e6123_61_65_switch_driver);
|
|
#endif
|
|
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
|
|
register_switch_driver(&mv88e6352_switch_driver);
|
|
#endif
|
|
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
|
|
register_switch_driver(&mv88e6171_switch_driver);
|
|
#endif
|
|
return 0;
|
|
}
|
|
module_init(mv88e6xxx_init);
|
|
|
|
static void __exit mv88e6xxx_cleanup(void)
|
|
{
|
|
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
|
|
unregister_switch_driver(&mv88e6171_switch_driver);
|
|
#endif
|
|
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
|
|
unregister_switch_driver(&mv88e6123_61_65_switch_driver);
|
|
#endif
|
|
#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
|
|
unregister_switch_driver(&mv88e6131_switch_driver);
|
|
#endif
|
|
}
|
|
module_exit(mv88e6xxx_cleanup);
|
|
|
|
MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
|
|
MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
|
|
MODULE_LICENSE("GPL");
|